View M36WT8B10ZA6T_3240038.PDF datasheet online --- IC-ON-LINE

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1/92 product preview july 2002 this is preliminary information on a new product now in development. details are subject to change without notice. m36wt864tf m36wt864bf 64 mbit (4mb x16, multiple bank, burst) flash memory and 8 mbit (512k x16) sram, multiple memory product features summary supply voltage Cv ddf = 1.65v to 2.2v Cv dds = v ddqf = 2.7v to 3.3v Cv ppf = 12v for fast program (optional) access time: 70, 85, 100ns low power consumption electronic signature C manufacturer code: 20h C top device code, m36wt864tf: 8810h C bottom device code, m36wt864bf: 8811h flash memory programming time C 8s by word typical for fast factory program C double/quadruple word program option C enhanced factory program options memory blocks C multiple bank memory array: 4 mbit banks C parameter blocks (top or bottom location) dual operations C program erase in one bank while read in others C no delay between read and write operations block locking C all blocks locked at power up C any combination of blocks can be locked Cwp for block lock-down security C 128 bit user programmable otp cells C 64 bit unique device number C one parameter block permanently lockable common flash interface (cfi) 100,000 program/erase cycles per block sram 8 mbit (512k x 16 bit) equal cycle and access times: 70ns low standby current low v dds data retention: 1.5v tri-state common i/o automatic power down figure 1. packages fbga stacked lfbga96 (za) 8 x 14mm
m36wt864tf, m36wt864bf 2/92 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. lfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 address inputs (a0-a18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 address inputs (a19-a21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 data input/output (dq0-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 flash chip enable (ef). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 flash output enable (gf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 flash write enable (wf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 flash write protect (wpf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 flash reset (rpf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 flash latch enable (lf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 flash clock (kf).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 flash wait (waitf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 sram chip enable (e1s, e2s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 sram write enable (ws). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 sram output enable (gs).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 sram upper byte enable (ubs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 sram lower byte enable (lbs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 v ddf supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 v ddqf and v dds supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 v ppf program supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 v ssf , v ssqf and v sss grounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2. main operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 flash memory component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 sram component. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. flash bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. flash block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 flash bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 bus write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 address latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 flash command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3/92 m36wt864tf, m36wt864bf table 4. command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 command interface - standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 read array command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 read status register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 read cfi query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 clear status register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 bank erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 protection register program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 set configuration register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 block lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 block unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 block lock-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. flash standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6. electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 6. flash security block and protection register memory map . . . . . . . . . . . . . . . . . . . . . . 22 command interface - factory program commands . . . . . . . . . . . . . . . . . . . . . . . . . 23 double word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 quadruple word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 enhanced factory program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 setup phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 program phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 quadruple enhanced factory program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 setup phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 load phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 program and verify phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 7. flash factory program commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 flash status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 program/erase controller status bit (sr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 erase suspend status bit (sr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 erase status bit (sr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 program status bit (sr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 v ppf status bit (sr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 program suspend status bit (sr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 block protection status bit (sr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 bank write/multiple word program status bit (sr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 8. flash status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
m36wt864tf, m36wt864bf 4/92 flash configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 read select bit (cr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 x-latency bits (cr13-cr11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 wait polarity bit (cr10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 data output configuration bit (cr9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 wait configuration bit (cr8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 burst type bit (cr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 valid clock edge bit (cr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 wrap burst bit (cr3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 burst length bits (cr2-cr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 9. flash configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 10. burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 7. x-latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 8. wait configuration example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 flash read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 asynchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 synchronous burst read mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 single synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 flash dual operations and multiple bank architecture. . . . . . . . . . . . . . . . . . . . . . 36 table 11. dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 12. dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 flash block locking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 reading a blocks lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 locking operations during erase suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 13. flash lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 flash program and erase times and endurance cycles. . . . . . . . . . . . . . . . . . . . . . . 39 table 14. flash program, erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 sram operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 standby/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 15. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5/92 m36wt864tf, m36wt864bf dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 16. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 9. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 10. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 17. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 18. flash dc characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 19. flash dc characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 20. sram dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 11. flash asynchronous random access read ac waveforms . . . . . . . . . . . . . . . . . . . . . 45 figure 12. flash asynchronous page read ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 21. flash asynchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 13. flash synchronous burst read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 14. flash single synchronous read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 15. flash clock input ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 22. flash synchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 16. flash write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 23. flash write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 17. flash write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 24. flash write ac characteristics, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 18. flash reset and power-up ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 25. flash reset and power-up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 19. sram address controlled, read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 20. sram chip enable or output enable controlled, read ac waveforms . . . . . . . . . . . . 56 figure 21. sram chip enable or ubs/lbs controlled, standby ac waveforms . . . . . . . . . . . . . 57 table 26. sram read and standby ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 22. sram write ac waveforms, write enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 23. sram write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 24. sram write ac waveforms, ub/lb controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 27. sram write ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 25. sram low vdd data retention ac waveforms, e1s controlled. . . . . . . . . . . . . . . . . 61 figure 26. sram low vdd data retention ac waveforms, e2s controlled. . . . . . . . . . . . . . . . . 61 table 28. sram low vdd data retention characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 27. stacked lfbga96 - 8x14mm, 8x10ball array, 0.8mm pitch, bottom view package outline 62 table 29. stacked lfbga96 - 8x14mm, 8x10 ball array, 0.8mm pitch, package mechanical data 62 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 30. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 31. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 appendix a. flash block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
m36wt864tf, m36wt864bf 6/92 table 32. flash top boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 33. flash bottom boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 appendix b. flash common flash interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 34. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 table 35. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 table 36. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 37. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 table 38. primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 39. protection register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 table 40. burst read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 41. bank and erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 42. bank and erase block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 43. bank and erase block region 2 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 appendix c. flash flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 28. program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 29. double word program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 30. quadruple word program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 31. program suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . 79 figure 32. block erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 33. erase suspend & resume flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . 81 figure 34. locking operations flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 35. protection register program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . 83 figure 36. enhanced factory program flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 enhanced factory program pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 37. quadruple enhanced factory program flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 quadruple enhanced factory program pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 appendix d. flash command interface state tables . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 44. command interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 45. command interface states - modify table, next output. . . . . . . . . . . . . . . . . . . . . . . . . 89 table 46. command interface states - lock table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 47. command interface states - lock table, next output . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7/92 m36wt864tf, m36wt864bf summary description the m36wt864 is a low voltage multiple memory product which combines two memory devices; a 64 mbit multiple bank flash memory and an 8 mbit sram. recommended operating conditions do not allow both the flash and the sram to be ac- tive at the same time. the memory is offered in a stacked lfbga96 (8 x 14mm, 0.8 mm pitch) package and is supplied with all the bits erased (set to 1). figure 2. logic diagram table 1. signal names ai06270 22 a0-a21 ef dq0-dq15 m36wt864tf m36wt864bf gf v ssf 16 wf rpf wpf e1s e2s gs ws ubs lbs v sss v ddf v ppf v dds waitf lf kf v ddqf v ssqf a0-a18 address inputs a19-a21 address inputs for flash chip only dq0-dq15 data input/output v ddf flash power supply v ddqf flash power supply for i/o buffers v ppf flash optional supply voltage for fast program & erase v ssf flash ground v ssqf flash ground for i/o buffers v dds sram power supply v sss sram ground nc not connected internally du do not use as internally connected flash control functions lf latch enable input ef chip enable input gf output enable input wf write enable input rpf reset input wpf write protect input kf flash burst clock waitf wait data in burst mode sram control functions e1s , e2s chip enable inputs gs output enable input ws write enable input ubs upper byte enable input lbs lower byte enable input
m36wt864tf, m36wt864bf 8/92 figure 3. lfbga connections (top view through package) 8 7 6 5 4 3 2 1 c b nc nc a21 kf a4 a11 d e f nc nc ws v sss a19 a18 nc v dds a5 a12 e2s v sss nc lbs a9 v ssf a3 a13 v ddf v ppf nc a17 a10 a20 a2 a15 lf wpf nc a7 a14 a8 a1 a16 wf rp ubs a6 waitf dq13 a0 du dq5 dq10 dq2 dq8 dq7 dq14 gs du dq12 dq3 dq1 dq0 dq15 dq6 e1s du dq4 dq11 dq9 gf v ddqf du ef v sss v dds v dds du du v ssf v ssqf v sss v sss v sss v ddf v ddqf v ssqf nc nc nc nc nc nc nc nc nc nc nc nc #a #b a g h j k ai06271 #c #d
9/92 m36wt864tf, m36wt864bf signal descriptions see figure 2 logic diagram and table 1,signal names, for a brief overview of the signals connect- ed to this device. address inputs (a0-a18). addresses a0-a18 are common inputs for the flash and the sram components. the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they con- trol the commands sent to the command interface of the internal state machine. the flash memory is accessed through the chip enable ( ef ) and write enable (wf ) signals, while the sram is accessed through two chip enable signals (e1s and e2s) and the write enable signal (ws ). address inputs (a19-a21). addresses a19-a21 are inputs for the flash component only. the flash memory is accessed through the chip en- able (ef ) and write enable (wf ) signals. data input/output (dq0-dq15). the data i/o outputs the data stored at the selected address during a bus read operation or inputs a command or the data to be programmed during a write bus operation. flash chip enable (ef ). the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. when chip en- able is at v il and reset is at v ih the device is in ac- tive mode. when chip enable is at v ih the memory is deselected, the outputs are high imped- ance and the power consumption is reduced to the stand-by level. flash output enable (gf ). the output enable controls data outputs during the bus read opera- tion of the memory. flash write enable ( wf ). the write enable controls the bus write operation of the memorys command interface. the data and address inputs are latched on the rising edge of chip enable or write enable whichever occurs first. flash write protect (wpf ). write protect is an input that gives an additional hardware protection for each block. when write protect is at v il , the lock-down is enabled and the protection status of the locked-down blocks cannot be changed. when write protect is at v ih , the lock-down is disabled and the locked-down blocks can be locked or unlocked. (refer to table 13, lock sta- tus). flash reset (rpf ). the reset input provides a hardware reset of the memory. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the reset supply current i dd2 . refer to table 2, dc characteristics - currents for the val- ue of i dd2. after reset all blocks are in the locked state and the configuration register is reset. when reset is at v ih , the device is in normal op- eration. exiting reset mode the device enters asynchronous read mode, but a negative transi- tion of chip enable or latch enable is required to ensure valid data outputs. the reset pin can be interfaced with 3v logic with- out any additional circuitry. it can be tied to v rph (refer to table 19, dc characteristics). flash latch enable (lf ). latch enable latches the address bits on its rising edge. the address latch is transparent when latch enable is at v il and it is inhibited when latch enable is at v ih . latch enable can be kept low (also at board level) when the latch enable function is not required or supported. flash clock (kf). the clock input synchronizes the flash memory to the microcontroller during synchronous read operations; the address is latched on a clock edge (rising or falling, accord- ing to the configuration settings) when latch en- able is at v il . clock is don't care during asynchronous read and in write operations. flash wait (waitf). wait is a flash output signal used during synchronous read to indicate whether the data on the output bus are valid. this output is high impedance when flash chip enable is at v ih or flash reset is at v il . it can be configured to be active during the wait cycle or one clock cycle in advance. the waitf signal is not gated by output enable. sram chip enable (e1s , e2s). the chip en- able inputs activate the sram memory control logic, input buffers and decoders. e1s at v ih or e2s at v il deselects the memory and reduces the power consumption to the standby level. e1s and e2s can also be used to control writing to the sram memory array, while ws remains at v il. it is not allowed to set ef at v il, e1s at v il and e2s at v ih at the same time. sram write enable (ws ). the write enable in- put controls writing to the sram memory array. ws is active low. sram output enable (gs) . the output enable gates the outputs through the data buffers during a read operation of the sram memory. gs is ac- tive low. sram upper byte enable (ubs) . the upper byte enable input enables the upper byte for sram (dq8-dq15). ubs is active low. sram lower byte enable (lbs ). the lower byte enable input enables the lower byte for sram (dq0-dq7). lbs is active low. v ddf supply voltage. v ddf provides the power supply to the internal core of the flash memory de-
m36wt864tf, m36wt864bf 10/92 vice. it is the main power supply for all flash oper- ations (read, program and erase). v ddqf and v dds supply voltage. v ddqf pro- vides the power supply for the flash memory i/o pins and v dds provides the power supply for the sram control and i/o pins. this allows all outputs to be powered independently from the flash core power supply, v ddf . v ddqf can be tied to v dds or it can use a separate supply. v ppf program supply voltage. v ppf is both a flash control input and a flash power supply pin. the two functions are selected by the voltage range applied to the pin. if v ppf is kept in a low voltage range (0v to v ddqf ) v ppf is seen as a control input. in this case a volt- age lower than v pplkf gives an absolute protec- tion against program or erase, while v ppf > v pp1f enables these functions (see tables 18 and 19, dc characteristics for the relevant values). v ppf is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. if v ppf is in the range of v pphf it acts as a power supply pin. in this condition v ppf must be stable until the program/erase algorithm is completed. v ssf , v ssqf and v sss grounds. v ssf , v ssqf and v sss are the ground references for all voltage measurements in the flash (core and i/o buffers) and sram chips, respectively. note: each device in a system should have v ddf and v ppf decoupled with a 0.1f ceramic capacitor close to the pin (high frequency, in- herently low inductance capacitors should be as close as possible to the package). see fig- ure 10, ac measurement load circuit. the pcb trace widths should be sufficient to carry the required v ppf program and erase currents.
11/92 m36wt864tf, m36wt864bf functional description the flash and sram components have separate power supplies and grounds and are distinguished by three chip enable inputs: ef for the flash mem- ory and, e1s and e2s for the sram. recommended operating conditions do not allow both the flash and the sram to be in active mode at the same time. the most common example is simultaneous read operations on the flash and the sram which would result in a data bus con- tention. therefore it is recommended to put the sram in the high impedance state when reading the flash and vice versa (see table 2 main oper- ation modes for details). figure 4. functional block diagram ai06272 flash memory 64 mbit (x16) v ssf rpf wpf e1s e2s gs ws dq0-dq15 v ddf v ppf a19-a21 a0-a18 sram 8 mbit (x 16) v sss v dds ef gf wf ubs lbs waitf kf lf v ddqf v ssqf
m36wt864tf, m36wt864bf 12/92 table 2. main operation modes note: 1. x = don't care. 2. l can be tied to v ih if the valid address has been previously latched. 3. depends on g . 4. wait signal polarity is configured using the set configuration register command. operation mode ef gf wf lf rpf waitf e1s e2s gs ws ubs , lbs dq15-dq0 flash memory bus read v il v il v ih v il (2) v ih sram must be disabled data output bus write v il v ih v il v il (2) v ih sram must be disabled data input address latch v il x v ih v il v ih sram must be disabled data output or hi-z (3) output disable v il v ih v ih x v ih sram must be disabled hi-z standby v ih xx x v ih hi-z any sram mode is allowed hi-z reset x x x x v il hi-z any sram mode is allowed hi-z sram read flash must be disabled v il v ih v il v ih v il data out word read write flash must be disabled v il v ih x v il v il data in word write standby/ power down any flash mode is allowable v ih x x x x hi-z x v il x x x hi-z xxxx v ih hi-z data retention any flash mode is allowable v ih v il x x x hi-z output disable any flash mode is allowable v il v ih v ih v ih x hi-z
13/92 m36wt864tf, m36wt864bf flash memory component the flash memory is a 64 mbit (4mbit x16) non- volatile flash memory that may be erased electri- cally at block level and programmed in-system on a word-by-word basis using a 1.65v to 2.2v v dd supply for the circuitry and a 1.65v to 3.3v v ddq supply for the input/output pins. an optional 12v v ppf power supply is provided to speed up cus- tomer programming. the device features an asymmetrical block archi- tecture with an array of 135 blocks divided into 4 mbit banks. there are 15 banks each containing 8 main blocks of 32 kwords, and one parameter bank containing 8 parameter blocks of 4 kwords and 7 main blocks of 32 kwords. the multiple bank architecture allows dual operations, while programming or erasing in one bank, read opera- tions are possible in other banks. only one bank at a time is allowed to be in program or erase mode. it is possible to perform burst reads that cross bank boundaries. the bank architecture is sum- marized in table 3, and the memory maps are shown in figure 5. the parameter blocks are lo- cated at the top of the memory address space for the m36wt864tf, and at the bottom for the m36wt864bf. each block can be erased separately. erase can be suspended, in order to perform program in any other block, and then resumed. program can be suspended to read data in any other block and then resumed. each block can be programmed and erased over 100,000 cycles using the supply voltage v dd . there are two enhanced factory programming commands available to speed up programming. program and erase commands are written to the command interface of the memory. an internal program/erase controller takes care of the tim- ings necessary for program and erase operations. the end of a program or erase operation can be detected and any error conditions identified in the status register. the command set required to control the memory is consistent with jedec stan- dards. the device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. in synchronous burst mode, data is output on each clock cycle at frequencies of up to 54mhz. the device features an automatic standby mode. during asynchronous read operations, after a bus inactivity of 150ns, the device automatically switches to the automatic standby mode. in this condition the power consumption is reduced to the standby value i dd4 and the outputs are still driven. the flash memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling in- stant code and data protection. all blocks have three levels of protection. they can be locked and locked-down individually preventing any acciden- tal programming or erasure. there is an additional hardware protection against program and erase. when v ppf v pplk all blocks are protected against program or erase. all blocks are locked at power- up. the device includes a protection register and a security block to increase the protection of a sys- tems design. the protection register is divided into two segments: a 64 bit segment containing a unique device number written by st, and a 128 bit segment one-time-programmable (otp) by the user. the user programmable segment can be permanently protected. the security block, pa- rameter block 0, can be permanently protected by the user. figure 6, shows the security block and protection register memory map. sram component the sram is an 8 mbit (512kb x16) asynchronous random access memory which features a super low voltage operation and low current consump- tion with an access time of 70ns. the memory op- erations can be performed using a single low voltage supply, 2.7v to 3.3v.
m36wt864tf, m36wt864bf 14/92 table 3. flash bank architecture figure 5. flash block addresses number bank size parameter blocks main blocks parameter bank 4 mbits 8 blocks of 4 kwords 7 blocks of 32 kwords bank 0 4 mbits - 8 blocks of 32 kwords bank 1 4 mbits - 8 blocks of 32 kwords bank 2 4 mbits - 8 blocks of 32 kwords ---- ---- ---- ---- bank 13 4 mbits - 8 blocks of 32 kwords bank 14 4 mbits - 8 blocks of 32 kwords ai06273 top boot block address lines a21-a0 8 main blocks bank 14 bottom boot block address lines a21-a0 32 kword 000000h 007fffh 32 kword 038000h 03ffffh 32 kword 300000h 307fffh 32 kword 338000h 33ffffh 32 kword 340000h 377fffh 32 kword 378000h 37ffffh 32 kword 380000h 387fffh 32 kword 3d8000h 3bffffh 32 kword 3c0000h 3c7fffh 32 kword 3f0000h 3f7fffh 4 kword 3f8000h 3f8fffh 4 kword 3ff000h 3fffffh 8 parameter blocks parameter bank parameter bank 4 kword 000000h 000fffh 4kword 007000h 007fffh 32 kword 008000h 00ffffh 32 kword 038000h 03ffffh 32 kword 040000h 047fffh 32 kword 078000h 07ffffh 32 kword 080000h 087fffh 32 kword 0b8000h 0bffffh 32 kword 0c0000h 0c7fffh 32 kword 0f8000h 0fffffh 32 kword 3c0000h 3c7fffh 32 kword 3f8000h 3fffffh bank 2 bank 1 bank 0 bank 14 bank 2 bank 1 bank 0 8 main blocks 8 main blocks 8 main blocks 7 main blocks 8 parameter blocks 7 main blocks 8 main blocks 8 main blocks 8 main blocks 8 main blocks
15/92 m36wt864tf, m36wt864bf flash bus operations there are six standard bus operations that control the flash device. these are bus read, bus write, address latch, output disable, standby and re- set. see table 2, main operating modes, for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus write operations. bus read. bus read operations are used to out- put the contents of the memory array, the elec- tronic signature, the status register and the common flash interface. both chip enable and output enable must be at v il in order to perform a read operation. the chip enable input should be used to enable the device. output enable should be used to gate data onto the output. the data read depends on the previous command written to the memory (see command interface section). see figures 11, 12, 13 and 14 read ac wave- forms, and tables 21 and 22 read ac character- istics, for details of when the output becomes valid. bus write. bus write operations write com- mands to the memory or latch input data to be programmed. a bus write operation is initiated when chip enable and write enable are at v il with output enable at v ih . commands, input data and addresses are latched on the rising edge of write enable or chip enable, whichever occurs first. the addresses can also be latched prior to the write operation by toggling latch enable. in this case the latch enable should be tied to v ih during the bus write operation. see figures 16 and 17, write ac waveforms, and tables 23 and 24, write ac characteristics, for details of the timing requirements. address latch. address latch operations input valid addresses. both chip enable and latch en- able must be at v il during address latch opera- tions. the addresses are latched on the rising edge of latch enable. output disable. the outputs are high imped- ance when the output enable is at v ih . standby. standby disables most of the internal circuitry allowing a substantial reduction of the cur- rent consumption. the memory is in stand-by when chip enable and reset are at v ih . the pow- er consumption is reduced to the stand-by level and the outputs are set to high impedance, inde- pendently from the output enable or write enable inputs. if chip enable switches to v ih during a pro- gram or erase operation, the device enters stand- by mode when finished. reset. during reset mode the memory is dese- lected and the outputs are high impedance. the memory is in reset mode when reset is at v il . the power consumption is reduced to the standby level, independently from the chip enable, output enable or write enable inputs. if reset is pulled to v ss during a program or erase, this operation is aborted and the memory content is no longer valid.
m36wt864tf, m36wt864bf 16/92 flash command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. an internal program/erase controller han- dles all timings and verifies the correct execution of the program and erase commands. the pro- gram/erase controller provides a status register whose output may be read at any time to monitor the progress or the result of the operation. the command interface is reset to read mode when power is first applied, when exiting from re- set or whenever v dd is lower than v lko . com- mand sequences must be followed exactly. any invalid combination of commands will reset the de- vice to read mode. refer to table 4, command codes and appendix d, tables 44, 45, 46 and 47, command interface states - modify and lock tables, for a summary of the command interface. the command interface is split into two types of commands: standard commands and factory program commands. the following sections ex- plain in detail how to perform each command. table 4. command codes hex code command 01h block lock confirm 03h set configuration register confirm 10h alternative program setup 20h block erase setup 2fh block lock-down confirm 30h enhanced factory program setup 35h double word program setup 40h program setup 50h clear status register 56h quadruple word program setup 60h block lock setup, block unlock setup, block lock down setup and set configuration register setup 70h read status register 75h quadruple enhanced factory program setup 80h bank erase setup 90h read electronic signature 98h read cfi query b0h program/erase suspend c0h protection register program d0h program/erase resume, block erase confirm, bank erase confirm, block unlock confirm or enhanced factory program confirm ffh read array
17/92 m36wt864tf, m36wt864bf command interface - standard commands the following commands are the basic commands used to read, write to and configure the device. refer to table 5, standard commands, in con- junction with the following text descriptions. read array command the read array command returns the addressed bank to read array mode. one bus write cycle is required to issue the read array command and re- turn the addressed bank to read array mode. subsequent read operations will read the ad- dressed location and output the data. a read ar- ray command can be issued in one bank while programming or erasing in another bank. however if a read array command is issued to a bank cur- rently executing a program or erase operation the command will be executed but the output data is not guaranteed. read status register command the status register indicates when a program or erase operation is complete and the success or failure of operation itself. issue a read status register command to read the status register content. the read status register command can be issued at any time, even during program or erase operations. the following read operations output the content of the status register of the addressed bank. the status register is latched on the falling edge of e or g signals, and can be read until e or g returns to v ih . either e or g must be toggled to update the latched data. see table 8 for the description of the status register bits. this mode supports asyn- chronous or single synchronous reads only. read electronic signature command the read electronic signature command reads the manufacturer and device codes, the block locking status, the protection register, and the configuration register. the read electronic signature command consists of one write cycle to an address within one of the banks. a subsequent read operation in the same bank will output the manufacturer code, the de- vice code, the protection status of the blocks in the targeted bank, the protection register, or the configuration register (see table 6). if a read electronic signature command is issued in a bank that is executing a program or erase op- eration the bank will go into read electronic sig- nature mode, subsequent bus read cycles will output the electronic signature data and the pro- gram/erase controller will continue to program or erase in the background. this mode supports asynchronous or single synchronous reads only, it does not support page mode or synchronous burst reads. read cfi query command the read cfi query command is used to read data from the common flash interface (cfi). the read cfi query command consists of one bus write cycle, to an address within one of the banks. once the command is issued subsequent bus read operations in the same bank read from the common flash interface. if a read cfi query command is issued in a bank that is executing a program or erase operation the bank will go into read cfi query mode, subse- quent bus read cycles will output the cfi data and the program/erase controller will continue to program or erase in the background. this mode supports asynchronous or single synchronous reads only, it does not support page mode or syn- chronous burst reads. the status of the other banks is not affected by the command (see table 11). after issuing a read cfi query command, a read array command should be issued to the addressed bank to return the bank to read array mode. see appendix c, common flash interface, tables 34, 35, 36, 37, 38, 40, 41, 42 and 43 for details on the information contained in the common flash in- terface memory area. clear status register command the clear status register command can be used to reset (set to 0) error bits 1, 3, 4 and 5 in the sta- tus register. one bus write cycle is required to is- sue the clear status register command. after the clear status register command the bank returns to read mode. the error bits in the status register do not auto- matically return to 0 when a new command is is- sued. the error bits in the status register should be cleared before attempting a new program or erase command. block erase command the block erase command can be used to erase a block. it sets all the bits within the selected block to 1. all previous data in the block is lost. if the block is protected then the erase operation will abort, the data in the block will not be changed and the status register will output the error. the block erase command can be issued at any moment, re- gardless of whether the block has been pro- grammed or not. two bus write cycles are required to issue the command. the first bus cycle sets up the erase command. the second latches the block address in the internal state machine and starts the program/ erase controller.
m36wt864tf, m36wt864bf 18/92 if the second bus cycle is not write erase confirm (d0h), status register bits 4 and 5 are set and the command aborts. erase aborts if reset turns to v il . as data integrity cannot be guaranteed when the erase operation is aborted, the block must be erased again. once the command is issued the device outputs the status register data when any address within the bank is read. at the end of the operation the bank will remain in read status register mode un- til a read array, read cfi query or read elec- tronic signature command is issued. during erase operations the bank containing the block being erased will only accept the read ar- ray, read status register, read electronic signa- ture, read cfi query and the program/erase suspend command, all other commands will be ig- nored. refer to dual operations section for de- tailed information about simultaneous operations allowed in banks not being erased. typical erase times are given in table 14, program, erase times and program/erase endurance cycles. see appendix c, figure 32, block erase flow- chart and pseudo code, for a suggested flowchart for using the block erase command. bank erase command the bank erase command can be used to erase a bank. it sets all the bits within the selected bank to 1. all previous data in the bank is lost. the bank erase command will ignore any protected blocks within the bank. if all blocks in the bank are pro- tected then the bank erase operation will abort and the data in the bank will not be changed. the status register will not output any error. two bus write cycles are required to issue the command. the first bus cycle sets up the bank erase command. the second latches the bank address in the internal state machine and starts the program/ erase controller. if the second bus cycle is not write bank erase confirm (d0h), status register bits sr4 and sr5 are set and the command aborts. erase aborts if reset turns to v il . as data integrity cannot be guaranteed when the erase operation is aborted, the bank must be erased again. once the command is issued the device outputs the status register data when any address within the bank is read. at the end of the operation the bank will remain in read status register mode un- til a read array, read cfi query or read elec- tronic signature command is issued. during bank erase operations the bank being erased will only accept the read array, read sta- tus register, read electronic signature and read cfi query command, all other commands will be ignored. a bank erase operation cannot be sus- pended. refer to dual operations section for detailed infor- mation about simultaneous operations allowed in banks not being erased. typical erase times are given in table 14, program, erase times and pro- gram/erase endurance cycles. program command the memory array can be programmed word-by- word. only one word in one bank can be pro- grammed at any one time. two bus write cycles are required to issue the program command. the first bus cycle sets up the program command. the second latches the address and the data to be written and starts the program/erase controller. after programming has started, read operations in the bank being programmed output the status register content. during program operations the bank being pro- grammed will only accept the read array, read status register, read electronic signature, read cfi query and the program/erase suspend com- mand. refer to dual operations section for de- tailed information about simultaneous operations allowed in banks not being programmed. typical program times are given in table 14, program, erase times and program/erase endurance cy- cles. programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the memory location must be reprogrammed. see appendix c, figure 28, program flowchart and pseudo code, for the flowchart for using the program command. program/erase suspend command the program/erase suspend command is used to pause a program or block erase operation. a bank erase operation cannot be suspended. one bus write cycle is required to issue the pro- gram/erase command. once the program/erase controller has paused bits sr7, sr6 and/ or sr2 of the status register will be set to 1. the com- mand can be addressed to any bank. during program/erase suspend the command in- terface will accept the program/erase resume, read array (cannot read the suspended block), read status register, read electronic signature and read cfi query commands. additionally, if the suspend operation was erase then the clear status register, program, block lock, block lock- down or block unlock commands will also be ac- cepted. the block being erased may be protected
19/92 m36wt864tf, m36wt864bf by issuing the block lock, block lock-down or protection register program commands. only the blocks not being erased may be read or pro- grammed correctly. when the program/erase re- sume command is issued the operation will complete. refer to the dual operations section for detailed information about simultaneous opera- tions allowed during program/erase suspend. during a program/erase suspend, the device can be placed in standby mode by taking chip enable to v ih . program/erase is aborted if reset turns to v il . see appendix c, figure 31, program suspend & resume flowchart and pseudo code, and figure 33, erase suspend & resume flowchart and pseudo code for flowcharts for using the program/ erase suspend command. program/erase resume command the program/erase resume command can be used to restart the program/erase controller after a program/erase suspend command has paused it. one bus write cycle is required to issue the command. the command can be written to any address. the program/erase resume command does not change the read mode of the banks. if the sus- pended bank was in read status register, read electronic signature or read cfi query mode the bank remains in that mode and outputs the corre- sponding data. if the bank was in read array mode subsequent read operations will output in- valid data. if a program command is issued during a block erase suspend, then the erase cannot be re- sumed until the programming operation has com- pleted. it is possible to accumulate suspend operations. for example: suspend an erase oper- ation, start a programming operation, suspend the programming operation then read the array. see appendix c, figure 31, program suspend & re- sume flowchart and pseudo code, and figure 33, erase suspend & resume flowchart and pseudo code for flowcharts for using the program/erase resume command. protection register program command the protection register program command is used to program the 128 bit user one-time-pro- grammable (otp) segment of the protection reg- ister and the protection register lock. the segment is programmed 16 bits at a time. when shipped all bits in the segment are set to 1. the user can only program the bits to 0. two write cycles are required to issue the protec- tion register program command. the first bus cycle sets up the protection register program command. the second latches the address and the data to be written to the protection register and starts the program/erase controller. read operations output the status register con- tent after the programming has started. the segment can be protected by programming bit 1 of the protection lock register. bit 1 of the pro- tection lock register also protects bit 2 of the pro- tection lock register. programming bit 2 of the protection lock register will result in a permanent protection of parameter block #0 (see figure 6, security block and protection register memory map). attempting to program a previously protect- ed protection register will result in a status reg- ister error. the protection of the protection register and/or the security block is not revers- ible. the protection register program cannot be sus- pended. see appendix c, figure 35, protection register program flowchart and pseudo code, for a flowchart for using the protection register program command. set configuration register command. the set configuration register command is used to write a new value to the burst configuration control register which defines the burst length, type, x latency, synchronous/asynchronous read mode and the valid clock edge configuration. two bus write cycles are required to issue the set configuration register command. the first cycle writes the setup command and the address corresponding to the configuration register content. the second cycle writes the configuration register data and the confirm command. once the command is issued the memory returns to read mode. the value for the configuration register is always presented on a0-a15. cr0 is on a0, cr1 on a1, etc.; the other address bits are ignored. block lock command the block lock command is used to lock a block and prevent program or erase operations from changing the data in it. all blocks are locked at power-up or reset. two bus write cycles are required to issue the block lock command. the first bus cycle sets up the block lock command. the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. table. 13 shows the lock status after issuing a block lock command.
m36wt864tf, m36wt864bf 20/92 the block lock bits are volatile, once set they re- main set until a hardware reset or power-down/ power-up. they are cleared by a block unlock command. refer to the section, block locking, for a detailed explanation. see appendix c, figure 34, locking operations flowchart and pseudo code, for a flowchart for using the lock command. block unlock command the block unlock command is used to unlock a block, allowing the block to be programmed or erased. two bus write cycles are required to is- sue the block unlock command. the first bus cycle sets up the block unlock command. the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. table 13 shows the protection status after issuing a block unlock command. refer to the section, block locking, for a detailed explanation and ap- pendix c, figure 34, locking operations flow- chart and pseudo code, for a flowchart for using the unlock command. block lock-down command a locked or unlocked block can be locked-down by issuing the block lock-down command. a locked- down block cannot be programmed or erased, or have its protection status changed when wp is low, v il . when wp is high, v ih, the lock-down function is disabled and the locked blocks can be individually unlocked by the block unlock com- mand. two bus write cycles are required to issue the block lock-down command. the first bus cycle sets up the block lock command. the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. locked-down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. table. 13 shows the lock status af- ter issuing a block lock-down command. refer to the section, block locking, for a detailed explana- tion and appendix c, figure 34, locking opera- tions flowchart and pseudo code, for a flowchart for using the lock-down command.
21/92 m36wt864tf, m36wt864bf table 5. flash standard commands note: 1. x = don't care, wa=word address in targeted bank, rd=read data, srd=status register data, esd=electronic signature data, qd=query data, ba=block address, bka= bank address, pd=program data, pra=protection register address, prd=protection register data, crd=configuration register data. 2. must be same bank as in the first cycle. the signature addresses are listed in table 6. commands cycles bus operations 1st cycle 2nd cycle op. add data op. add data read array 1+ write bka ffh read wa rd read status register 1+ write bka 70h read bka (2) srd read electronic signature 1+ write bka 90h read bka (2) esd read cfi query 1+ write bka 98h read bka (2) qd clear status register 1 write bka 50h block erase 2 write bka 20h write ba d0h bank erase 2 write bka 80h write bka d0h program 2 write bka 40h or 10h write wa pd program/erase suspend 1 write x b0h program/erase resume 1 write x d0h protection register program 2 write pra c0h write pra prd set configuration register 2 write crd 60h write crd 03h block lock 2 write bka 60h write ba 01h block unlock 2 write bka 60h write ba d0h block lock-down 2 write bka 60h write ba 2fh
m36wt864tf, m36wt864bf 22/92 table 6. electronic signature codes note: cr=configuration register. figure 6. flash security block and protection register memory map code address (h) data (h) manufacturer code bank address + 00 0020 device code top bank address + 01 8810 bottom bank address + 01 8811 block protection lock block address + 02 0001 unlocked 0000 locked and locked-down 0003 unlocked and locked-down 0002 reserved bank address + 03 reserved configuration register bank address + 05 cr protection register lock st factory default bank address + 80 0006 security block permanently locked 0002 otp area permanently locked 0004 security block and otp area permanently locked 0000 protection register bank address + 81 bank address + 84 unique device number bank address + 85 bank address + 8c otp area ai06181 parameter block # 0 user programmable otp unique device number protection register lock 2 1 0 8ch 85h 84h 81h 80h protection register security block
23/92 m36wt864tf, m36wt864bf command interface - factory program commands the factory program commands are used to speed up programming. they require v ppf to be at v pph . refer to table 7, factory program com- mands, in conjunction with the following text de- scriptions. double word program command the double word program command improves the programming throughput by writing a page of two adjacent words in parallel. the two words must differ only for the address a0. programming should not be attempted when v ppf is not at v pph . the command can be executed if v ppf is below v pph but the result is not guaran- teed. three bus write cycles are necessary to issue the double word program command. the first bus cycle sets up the double word program command. the second bus cycle latches the address and the data of the first word to be written. the third bus cycle latches the address and the data of the second word to be written and starts the program/erase controller. read operations in the bank being programmed output the status register content after the pro- gramming has started. during double word program operations the bank being programmed will only accept the read ar- ray, read status register, read electronic signa- ture and read cfi query command, all other commands will be ignored. dual operations are not supported during double word program oper- ations and it is not recommended to suspend a double word program operation. typical program times are given in table 14, program, erase times and program/erase endurance cycles. programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. see appendix c, figure 29, double word pro- gram flowchart and pseudo code, for the flow- chart for using the double word program command. quadruple word program command the quadruple word program command im- proves the programming throughput by writing a page of four adjacent words in parallel. the four words must differ only for the addresses a0 and a1. programming should not be attempted when v ppf is not at v pph . the command can be executed if v ppf is below v pph but the result is not guaran- teed. five bus write cycles are necessary to issue the quadruple word program command. the first bus cycle sets up the double word program command. the second bus cycle latches the address and the data of the first word to be written. the third bus cycle latches the address and the data of the second word to be written. the fourth bus cycle latches the address and the data of the third word to be written. the fifth bus cycle latches the address and the data of the fourth word to be written and starts the program/erase controller. read operations to the bank being programmed output the status register content after the pro- gramming has started. programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. during quadruple word program operations the bank being programmed will only accept the read array, read status register, read electronic sig- nature and read cfi query command, all other commands will be ignored. dual operations are not supported during quadru- ple word program operations and it is not recom- mended to suspend a quadruple word program operation. typical program times are given in ta- ble 14, program, erase times and program/erase endurance cycles. see appendix c, figure 30, quadruple word pro- gram flowchart and pseudo code, for the flow- chart for using the quadruple word program command. enhanced factory program command the enhanced factory program command can be used to program large streams of data within any one block. it greatly reduces the total program- ming time when a large number of words are writ- ten to a block at any one time. the use of the enhanced factory program com- mand requires certain operating conditions. v ppf must be set to v pph v dd must be within operating range ambient temperature, t a must be 25c 5c the targeted block must be unlocked dual operations are not supported during the en- hanced factory program operation and the com- mand cannot be suspended. for optimum performance the enhanced factory program commands should be limited to a maxi- mum of 10 program/erase cycles per block. if this
m36wt864tf, m36wt864bf 24/92 limit is exceeded the internal algorithm will contin- ue to work properly but some degradation in per- formance is possible. typical program times are given in table 14. the enhanced factory program command has four phases: the setup phase, the program phase to program the data to the memory, the verify phase to check that the data has been correctly programmed and reprogram if necessary and the exit phase. refer to table 7, enhanced factory program command and figure 36, enhanced factory program flowchart. setup phase. the enhanced factory program command requires two bus write operations to ini- tiate the command. the first bus cycle sets up the enhanced factory program command. the second bus cycle confirms the command. the status register p/e.c. bit 7 should be read to check that the p/e.c. is ready. after the confirm command is issued, read operations output the status register data. the read status register command must not be issued as it will be interpreted as data to program. program phase. the program phase requires n+1 cycles, where n is the number of words (refer to table 7, enhanced factory program command and figure 36, enhanced factory program flow- chart). three successive steps are required to issue and execute the program phase of the command. 1. use one bus write operation to latch the start address and the first word to be programmed. the status register bank write status bit sr0 should be read to check that the p/e.c. is ready for the next word. 2. each subsequent word to be programmed is latched with a new bus write operation. the address can either remain the start address, in which case the p/e.c. increments the address location or the address can be incremented in which case the p/e.c. jumps to the new address. if any address that is not in the same block as the start address is given with data ffffh, the program phase terminates and the verify phase begins. the status register bit sr0 should be read between each bus write cycle to check that the p/e.c. is ready for the next word. 3. finally, after all words have been programmed, write one bus write operation with data ffffh to any address outside the block containing the start address, to terminate the programming phase. if the data is not ffffh, the command is ignored. the memory is now set to enter the verify phase. verify phase. the verify phase is similar to the program phase in that all words must be resent to the memory for them to be checked against the programmed data. the program/erase controller checks the stream of data with the data that was programmed in the program phase and repro- grams the memory location if necessary. three successive steps are required to execute the verify phase of the command. 1. use one bus write operation to latch the start address and the first word, to be verified. the status register bit sr0 should be read to check that the program/erase controller is ready for the next word. 2. each subsequent word to be verified is latched with a new bus write operation. the words must be written in the same order as in the program phase. the address can remain the start address or be incremented. if any address that is not in the same block as the start address is given, the verify phase terminates. status register bit sr0 should be read to check that the p/e.c. is ready for the next word. 3. finally, after all words have been verified, write one bus write operation with data ffffh to any address outside the block containing the start address, to terminate the verify phase. if the verify phase is successfully completed the memory returns to the read mode. if the program/ erase controller fails to reprogram a given loca- tion, the error will be signaled in the status regis- ter. exit phase. status register p/e.c. bit sr7 set to 1 indicates that the device has returned to read mode. a full status register check should be done to ensure that the block has been successfully pro- grammed. see the section on the status register for more details. quadruple enhanced factory program command the quadruple enhanced factory program com- mand can be used to program one or more pages of four adjacent words in parallel. the four words must differ only for the addresses a0 and a1. v ppf must be set to v pph during quadruple enhanced factory program. it has four phases: the setup phase, the load phase where the data is loaded into the buffer, the combined program and verify phase where the loaded data is programmed to the memory and then automatically checked and reprogrammed if necessary and the exit phase. unlike the en- hanced factory program it is not necessary to re- submit the data for the verify phase. the load phase and the program and verify phase can be repeated to program any number of pages within the block.
25/92 m36wt864tf, m36wt864bf setup phase. the quadruple enhanced factory program command requires one bus write opera- tion to initiate the load phase. after the setup command is issued, read operations output the status register data. the read status register command must not be issued as it will be interpreted as data to program. load phase. the load phase requires 4 cycles to load the data (refer to table 7, factory program commands and figure 37, quadruple enhanced factory program flowchart). once the first word of each page is written it is impossible to exit the load phase until all four words have been written. two successive steps are required to issue and execute the load phase of the quadruple en- hanced factory program command. 1. use one bus write operation to latch the start address and the first word of the first page to be programmed. for subsequent pages the first word address can remain the start address (in which case the next page is programmed) or can be any address in the same block. if any address is given that is not in the same block as the start address, the device enters the exit phase. for the first load phase status register bit sr7 should be read after the first word has been issued to check that the command has been accepted (bit 7 set to 0). this check is not required for subsequent load phases. status register bit sr0 should be read to check that the p/e.c. is ready for the next word. 2. each subsequent word to be programmed is latched with a new bus write operation. the address is only checked for the first word of each page as the order of the words to be programmed is fixed. the status register bit sr0 should be read between each bus write cycle to check that the p/e.c. is ready for the next word. the memory is now set to enter the program and verify phase. program and verify phase. in the program and verify phase the four words that were loaded in the load phase are programmed in the memory array and then verified by the program/erase con- troller. if any errors are found the program/erase controller reprograms the location. during this phase the status register shows that the pro- gram/erase controller is busy, status register bit sr7 set to 0, and that the device is not waiting for new data, status register bit sr0 set to 1. when status register bit sr0 is set to 0 the program and verify phase has terminated. once the verify phase has successfully complet- ed subsequent pages in the same block can be loaded and programmed. the device returns to the beginning of the load phase by issuing one bus write operation to latch the address and the first of the four new words to be programmed. exit phase. finally, after all the pages have been programmed, write one bus write operation with data ffffh to any address outside the block con- taining the start address, to terminate the load and program and verify phases. if the program and verify phase has successfully completed the memory returns to read mode. if the p/e.c. fails to program and reprogram a given location, the error will be signaled in the status register. status register bit sr7 set to 1 and bit 0 set to 0 indicate that the device has returned to read mode. a full status register check should be done to ensure that the block has been successfully pro- grammed. see the section on the status register for more details.
m36wt864tf, m36wt864bf 26/92 table 7. flash factory program commands note: 1. wa=word address in targeted bank, bka= bank address, pd=program data, ba=block address. 2. wa1 is the start address. not wa1 is any address that is not in the same block as wa1. 3. address can remain starting address wa1 or be incremented. 4. word addresses 1 and 2 must be consecutive addresses differing only for a0. 5. word addresses 1,2,3 and 4 must be consecutive addresses differing only for a0 and a1. 6. a bus read must be done between each write cycle where the data is programmed or verified to read the status register and check that the memory is ready to accept the next data. n = number of words, i = number of pages to be programmed. 7. address is only checked for the first word of each page as the order to program the words in each page is fixed so subsequent words in each page can be written to any address. command phase cycles bus write operations 1st 2nd 3rd final -1 final add data add data add data add data add data double word program (4) 3 bka 35h wa1 pd1 wa2 pd2 quadruple word program (5) 5 bka 56h wa1 pd1 wa2 pd2 wa3 pd3 wa4 pd4 enhanced factory program (6) setup, program 2 +n +1 bka 30h ba d0h wa1 (2) pd1 wan (3) pan not wa1 (2) ffffh verify, exit n +1 wa1 (2) pd1 wa2 (3) pd2 wa3 (3) pd3 wan (3) pan not wa1 (2) ffffh quadruple enhanced factory program (5,6) setup, first load 5 bka 75h wa1 (2) pd1 wa2 (7) pd2 wa3 (7) pd3 wa4 (7) pd4 first program & verify automatic subsequent loads 4 wa1i (2) pd1i wa2i (7) pd2i wa3i (7) pd3i wa4i (7) pd4i subsequent program & verify automatic exit 1 not wa1 (2) ffffh
27/92 m36wt864tf, m36wt864bf flash status register the flash memory contains a status register which provides information on the current or previ- ous program or erase operations. issue a read status register command to read the contents of the status register, refer to read status register command section for more details. to output the contents, the status register is latched and updat- ed on the falling edge of the chip enable or output enable signals and can be read until chip enable or output enable returns to v ih . the status reg- ister can only be read using single asynchronous or single synchronous reads. bus read opera- tions from any address within the bank, always read the status register during program and erase operations. the various bits convey information about the sta- tus and any errors of the operation. bits sr7, sr6, sr2 and sr0 give information on the status of the device and are set and reset by the device. bits sr5, sr4, sr3 and sr1 give information on er- rors, they are set by the device but must be reset by issuing a clear status register command or a hardware reset. if an error bit is set to 1 the status register should be reset before issuing another command. sr7 to sr1 refer to the status of the device while sr0 refers to the status of the ad- dressed bank. the bits in the status register are summarized in table 8, status register bits. refer to table 8 in conjunction with the following text descriptions. program/erase controller status bit (sr7). the program/erase controller status bit indicates whether the program/erase controller is active or inactive in any bank. when the program/erase controller status bit is low (set to 0), the pro- gram/erase controller is active; when the bit is high (set to 1), the program/erase controller is inactive, and the device is ready to process a new command. the program/erase controller status is low im- mediately after a program/erase suspend com- mand is issued until the program/erase controller pauses. after the program/erase controller paus- es the bit is high. during program, erase, operations the program/ erase controller status bit can be polled to find the end of the operation. other bits in the status reg- ister should not be tested until the program/erase controller completes the operation and the bit is high. after the program/erase controller completes its operation the erase status, program status, v ppf status and block lock status bits should be tested for errors. erase suspend status bit (sr6). the erase suspend status bit indicates that an erase opera- tion has been suspended or is going to be sus- pended in the addressed block. when the erase suspend status bit is high (set to 1), a program/ erase suspend command has been issued and the memory is waiting for a program/erase re- sume command. the erase suspend status should only be consid- ered valid when the program/erase controller sta- tus bit is high (program/erase controller inactive). sr7 is set within the erase suspend latency time of the program/erase suspend command being issued therefore the memory may still complete the operation rather than entering the suspend mode. when a program/erase resume command is is- sued the erase suspend status bit returns low. erase status bit (sr5). the erase status bit can be used to identify if the memory has failed to verify that the block or bank has erased correctly. when the erase status bit is high (set to 1), the program/erase controller has applied the maxi- mum number of pulses to the block or bank and still failed to verify that it has erased correctly. the erase status bit should be read once the program/ erase controller status bit is high (program/erase controller inactive). once set high, the erase status bit can only be re- set low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program status bit (sr4). the program status bit is used to identify a program failure. when the program status bit is high (set to 1), the pro- gram/erase controller has applied the maximum number of pulses to the byte and still failed to ver- ify that it has programmed correctly. the program status bit should be read once the program/erase controller status bit is high (program/erase con- troller inactive). once set high, the program status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new command is issued, otherwise the new command will appear to fail. v ppf status bit (sr3). the v ppf status bit can be used to identify an invalid voltage on the v ppf pin during program and erase operations. the v ppf pin is only sampled at the beginning of a pro- gram or erase operation. indeterminate results can occur if v ppf becomes invalid during an oper- ation. when the v ppf status bit is low (set to 0), the voltage on the v ppf pin was sampled at a valid voltage; when the v ppf status bit is high (set to 1), the v ppf pin has a voltage that is below the
m36wt864tf, m36wt864bf 28/92 v ppf lockout voltage, v pplk , the memory is pro- tected and program and erase operations cannot be performed. once set high, the v ppf status bit can only be re- set low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program suspend status bit (sr2). the pro- gram suspend status bit indicates that a program operation has been suspended in the addressed block. when the program suspend status bit is high (set to 1), a program/erase suspend com- mand has been issued and the memory is waiting for a program/erase resume command. the pro- gram suspend status should only be considered valid when the program/erase controller status bit is high (program/erase controller inactive). sr2 is set within the program suspend latency time of the program/erase suspend command be- ing issued therefore the memory may still com- plete the operation rather than entering the suspend mode. when a program/erase resume command is is- sued the program suspend status bit returns low. block protection status bit (sr1). the block protection status bit can be used to identify if a program or block erase operation has tried to modify the contents of a locked block. when the block protection status bit is high (set to 1), a program or erase operation has been at- tempted on a locked block. once set high, the block protection status bit can only be reset low by a clear status register com- mand or a hardware reset. if set high it should be reset before a new command is issued, otherwise the new command will appear to fail. bank write/multiple word program status bit (sr0). the bank write status bit indicates wheth- er the addressed bank is programming or erasing. in enhanced factory program mode the multiple word program bit shows if a word has finished programming or verifying depending on the phase. the bank write status bit should only be consid- ered valid when the program/erase controller sta- tus sr7 is low (set to 0). when both the program/erase controller status bit and the bank write status bit are low (set to 0), the addressed bank is executing a program or erase operation. when the program/erase con- troller status bit is low (set to 0) and the bank write status bit is high (set to 1), a program or erase operation is being executed in a bank other than the one being addressed. in enhanced factory program mode if multiple word program status bit is low (set to 0), the de- vice is ready for the next word, if the multiple word program status bit is high (set to 1) the device is not ready for the next word. note: refer to appendix c, flowcharts and pseu- do codes, for using the status register.
29/92 m36wt864tf, m36wt864bf table 8. flash status register bits note: logic level '1' is high, '0' is low. bit name type logic level definition sr7 p/e.c. status status '1' ready '0' busy sr6 erase suspend status status '1' erase suspended '0' erase in progress or completed sr5 erase status error '1' erase error '0' erase success sr4 program status error '1' program error '0' program success sr3 v ppf status error '1' v ppf invalid, abort '0' v ppf ok sr2 program suspend status status '1' program suspended '0' program in progress or completed sr1 block protection status error '1' program/erase on protected block, abort '0' no operation to protected blocks sr0 bank write status status '0' sr7 = 0 program or erase operation in addressed bank sr7 = 1 no program or erase operation in the device '1' sr7 = 0 program or erase operation in a bank other than the addressed bank sr7 = 1 not allowed multiple word program status (enhanced factory program mode) status '1' sr7 = 0 the device is not ready for the next word sr7 = 1 not allowed '0' sr7 = 0 the device is ready for the next word sr7 = 1 the device is exiting from efp
m36wt864tf, m36wt864bf 30/92 flash configuration register the flash memory contains a configuration reg- ister which is used to configure the type of bus ac- cess that the memory will perform. refer to read modes section for details on read operations. the configuration register is set through the command interface. after a reset or power-up the device is configured for asynchronous page read (cr15 = 1). the configuration register bits are described in table 9. they specify the selec- tion of the burst length, burst type, burst x latency and the read operation. refer to figures 7 and 8 for examples of synchronous burst configurations. read select bit (cr15) the read select bit, cr15, is used to switch be- tween asynchronous and synchronous bus read operations. when the read select bit is set to 1, read operations are asynchronous; when the read select bit is set to 0, read operations are synchronous. synchronous burst read is support- ed in both parameter and main blocks and can be performed across banks. on reset or power-up the read select bit is set to1 for asynchronous access. x-latency bits (cr13-cr11) the x-latency bits are used during synchronous read operations to set the number of clock cycles between the address being latched and the first data becoming available. for correct operation the x-latency bits can only assume the values in ta- ble 9, configuration register. the correspondence between x-latency settings and the maximum sustainable frequency must be calculated taking into account some system pa- rameters. two conditions must be satisfied: 1. depending on whether t avk_cpu or t delay is supplied either one of the following two equations must be satisfied: (n + 1) t k t acc - t avk_cpu + t qvk_cpu (n + 2) t k t acc + t delay + t qvk_cpu 2. and also t k > t kqv + t qvk_cpu where n is the chosen x-latency configuration code t k is the clock period t avk_cpu is clock to address valid, l low, or e low, whichever occurs last t delay is address valid, l low, or e low to clock, whichever occurs last t qvk_cpu is the data setup time required by the system cpu, t kqv is the clock to data valid time t acc is the random access time of the device. refer to figure 7, x-latency and data output configuration example. wait polarity bit (cr10) in synchronous burst mode the wait signal indi- cates whether the output data are valid or a wait state must be inserted. the wait polarity bit is used to set the polarity of the wait signal. when the wait polarity bit is set to 0 the wait signal is active low. when the wait polarity bit is set to 1 the wait signal is active high (default). data output configuration bit (cr9) the data output configuration bit determines whether the output remains valid for one or two clock cycles. when the data output configuration bit is 0 the output data is valid for one clock cycle, when the data output configuration bit is 1 the output data is valid for two clock cycles. the data output configuration depends on the condition: t k > t kqv + t qvk_cpu where t k is the clock period, t qvk_cpu is the data setup time required by the system cpu and t kqv is the clock to data valid time. if this condition is not satisfied, the data output configuration bit should be set to 1 (two clock cycles). refer to figure 7, x-latency and data output configuration exam- ple. wait configuration bit (cr8) in burst mode the wait bit controls the timing of the wait output pin, wait. when the wait bit is 0 the wait output pin is asserted during the wait state. when the wait bit is 1 (default) the wait output pin is asserted one clock cycle before the wait state. wait is asserted during a continuous burst and also during a 4 or 8 burst length if no-wrap config- uration is selected. wait is not asserted during asynchronous reads, single synchronous reads or during latency in synchronous reads. burst type bit (cr7) the burst type bit is used to configure the se- quence of addresses read as sequential or inter- leaved. when the burst type bit is 0 the memory outputs from interleaved addresses; when the burst type bit is 1 (default) the memory outputs from sequential addresses. see tables 10, burst type definition, for the sequence of addresses output from a given starting address in each mode. valid clock edge bit (cr6) the valid clock edge bit, cr6, is used to config- ure the active edge of the clock, k, during syn- chronous burst read operations. when the valid clock edge bit is 0 the falling edge of the clock is
31/92 m36wt864tf, m36wt864bf the active edge; when the valid clock edge bit is 1 the rising edge of the clock is active. wrap burst bit (cr3) the burst reads can be confined inside the 4 or 8 word boundary (wrap) or overcome the boundary (no wrap). the wrap burst bit is used to select be- tween wrap and no wrap. when the wrap burst bit is set to 0 the burst read wraps; when it is set to 1 the burst read does not wrap. burst length bits (cr2-cr0) the burst length bits set the number of words to be output during a synchronous burst read oper- ation as result of a single address latch cycle. they can be set for 4 words, 8 words or continu- ous burst, where all the words are read sequential- ly. in continuous burst mode the burst sequence can cross bank boundaries. in continuous burst mode or in 4, 8 words no-wrap, depending on the starting address, the device as- serts the wait output to indicate that a delay is necessary before the data is output. if the starting address is aligned to a 4 word boundary no wait states are needed and the wait output is not asserted. if the starting address is shifted by 1,2 or 3 posi- tions from the four word boundary, wait will be asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 64 word boundary, to indicate that the device needs an internal delay to read the successive words in the array. wait will be asserted only once during a continuous burst access. see also table 10, burst type definition. cr14, cr5 and cr4 are reserved for future use.
m36wt864tf, m36wt864bf 32/92 table 9. flash configuration register bit description value description cr15 read select 0 synchronous read 1 asynchronous read (default at power-on) cr14 reserved cr13-cr11 x-latency 010 2 clock latency 011 3 clock latency 100 4 clock latency 101 5 clock latency 111 reserved other configurations reserved cr10 wait polarity 0 wait is active low 1 wait is active high (default) cr9 data output configuration 0 data held for one clock cycle 1 data held for two clock cycles cr8 wait configuration 0 wait is active during wait state 1 wait is active one data cycle before wait state (default) cr7 burst type 0 interleaved 1 sequential (default) cr6 valid clock edge 0 falling clock edge 1 rising clock edge cr5-cr4 reserved cr3 wrap burst 0 wrap 1 no wrap cr2-cr0 burst length 001 4 words 010 8 words 111 continuous (cr7 must be set to 1)
33/92 m36wt864tf, m36wt864bf table 10. burst type definition mode start address 4 words 8 words continuous burst sequential interleaved sequential interleaved wrap 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6... 1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7... 2 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8... 3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9... ... 7 7-4-5-6 7-6-5-4 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13... ... 60 60-61-62-63-64-65-66... 61 61-62-63-wait-64-65-66... 62 62-63-wait-wait-64-65-66... 63 63-wait-wait-wait-64-65- 66... sequential interleaved sequential interleaved no-wrap 0 0-1-2-3 0-1-2-3-4-5-6-7 same as for wrap (wrap /no wrap has no effect on continuous burst ) 1 1-2-3-4 1-2-3-4-5-6-7-8 2 2-3-4-5 2-3-4-5-6-7-8-9... 3 3-4-5-6 3-4-5-6-7-8-9-10 ... 7 7-8-9-10 7-8-9-10-11-12-13-14 ... 60 60-61-62-63 60-61-62-63-64-65-66- 67 61 61-62-63-wait-64 61-62-63-wait-64-65- 66-67-68 62 62-63-wait- wait-64-65 62-63-wait-wait-64- 65-66-67-68-69 63 63-wait-wait- wait-64-65-66 63-wait-wait-wait- 64-65-66-67-68-69-70
m36wt864tf, m36wt864bf 34/92 figure 7. x-latency and data output configuration example figure 8. wait configuration example ai06182 a21-a0 valid address k l dq15-dq0 valid data x-latency valid data tacc tavk_cpu tk tqvk_cpu tqvk_cpu tkqv 1st cycle 2nd cycle 3rd cycle 4th cycle note. settings shown: x-latency = 4, data output held for one clock cycle e tdelay ai06972 a21-a0 valid address k l dq15-dq0 valid data wait cr8 = '0' cr10 = '0' wait cr8 = '1' cr10 = '0' valid data not valid valid data e wait cr8 = '0' cr10 = '1' wait cr8 = '1' cr10 = '1'
35/92 m36wt864tf, m36wt864bf flash read modes flash read operations can be performed in two different ways depending on the settings in the configuration register. if the clock signal is dont care for the data output, the read operation is asynchronous; if the data output is synchronized with clock, the read operation is synchronous. the read mode and data output format are deter- mined by the configuration register. (see config- uration register section for details). all banks supports both asynchronous and synchronous read operations. the multiple bank architecture allows read operations in one bank, while write op- erations are being executed in another (see ta- bles 11 and 12). asynchronous read mode in asynchronous read operations the clock signal is dont care. the device outputs the data corre- sponding to the address latched, that is the mem- ory array, status register, common flash interface or electronic signature depending on the command issued. cr15 in the configuration reg- ister must be set to 1 for asynchronous opera- tions. in asynchronous read mode a page of data is in- ternally read and stored in a page buffer. the page has a size of 4 words and is addressed by a0 and a1 address inputs. the address inputs a0 and a1 are not gated by latch enable in asyn- chronous read mode. the first read operation within the page has a longer access time (t acc , random access time), subsequent reads within the same page have much shorter access times. if the page changes then the normal, longer timings apply again. asynchronous read operations can be performed in two different ways, asynchronous random ac- cess read and asynchronous page read. only asynchronous page read takes full advantage of the internal page storage so different timings are applied. see table 21, asynchronous read ac character- istics, figure 11, asynchronous random access read ac waveform and figure 12, asynchronous page read ac waveform for details. synchronous burst read mode in synchronous burst read mode the data is out- put in bursts synchronized with the clock. it is pos- sible to perform burst reads across bank boundaries. synchronous burst read mode can only be used to read the memory array. for other read opera- tions, such as read status register, read cfi and read electronic signature, single synchro- nous read or asynchronous random access read must be used. in synchronous burst read mode the flow of the data output depends on parameters that are con- figured in the configuration register. a burst sequence is started at the first clock edge (rising or falling depending on valid clock edge bit cr6 in the configuration register) after the falling edge of latch enable. addresses are internally in- cremented and after a delay of 2 to 5 clock cycles (x latency bits cr13-cr11) the corresponding data are output on each clock cycle. the number of words to be output during a syn- chronous burst read operation can be configured as 4 or 8 words or continuous (burst length bits cr2-cr0). the data can be configured to remain valid for one or two clock cycles (data output con- figuration bit cr9). the order of the data output can be modified through the burst type and the wrap burst bits in the configuration register. the burst sequence may be configured to be sequential or interleaved (cr7). the burst reads can be confined inside the 4 or 8 word boundary (wrap) or overcome the boundary (no wrap). if the starting address is aligned to a 4 word page the wrapped configura- tion has no impact on the output sequence. inter- leaved mode is not allowed in continuous burst read mode or with no wrap sequences. a wait signal may be asserted to indicate to the system that an output delay will occur. this delay will depend on the starting address of the burst se- quence; the worst case delay will occur when the sequence is crossing a 64 word boundary and the starting address was at the end of a four word boundary. wait is asserted during x latency and the wait state and is only deasserted when output data are valid. in continuous burst read mode a wait state will occur when crossing the first 64 word bound- ary. if the burst starting address is aligned to a 4 word page, the wait state will not occur. the wait signal can be configured to be active low or active high (default) by setting cr10 in the configuration register. the wait signal is mean- ingful only in synchronous burst read mode, in other modes, wait is always asserted (except for read array mode). see table 22, synchronous read ac character- istics and figure 13, synchronous burst read ac waveform for details. single synchronous read mode single synchronous read operations are similar to synchronous burst read operations except that only the first data output after the x latency is valid. other configuration register parameters have no effect on single synchronous read operations.
m36wt864tf, m36wt864bf 36/92 synchronous single reads are used to read the electronic signature, status register, cfi, block protection status, configuration register status or protection register. when the addressed bank is in read cfi, read status register or read electronic signature mode, the wait signal is al- ways asserted. see table 22, synchronous read ac character- istics and figure 14, single synchronous read ac waveform for details. flash dual operations and multiple bank architecture the multiple bank architecture of the flash mem- ory provides flexibility for software developers by allowing code and data to be split with 4mbit gran- ularity. the dual operations feature simplifies the software management of the device and allows code to be executed from one bank while another bank is being programmed or erased. the dual operations feature means that while pro- gramming or erasing in one bank, read opera- tions are possible in another bank with zero latency (only one bank at a time is allowed to be in program or erase mode). if a read operation is re- quired in a bank which is programming or erasing, the program or erase operation can be suspend- ed. also if the suspended operation was erase then a program command can be issued to anoth- er block, so the device can have one block in erase suspend mode, one programming and oth- er banks in read mode. bus read operations are allowed in another bank between setup and con- firm cycles of program or erase operations. the combination of these features means that read op- erations are possible at any moment. tables 11 and 12 show the dual operations possi- ble in other banks and in the same bank. note that only the commonly used commands are repre- sented in these tables. for a complete list of pos- sible commands refer to appendix d, command interface state tables. table 11. dual operations allowed in other banks table 12. dual operations allowed in same bank note: 1. not allowed in the block or word that is being erased or programmed. 2. the read array command is accepted but the data output is not guaranteed until the program or erase has completed. status of bank commands allowed in another bank read array read status register read cfi query read electronic signature program erase program/ erase suspend program/ erase resume idle yes yes yes yes yes yes yes yes programming yes yes yes yes C C yes C erasing yes yes yes yes C C yes C program suspended yes yes yes yes C C C yes erase suspended yes yes yes yes yes C C yes status of bank commands allowed in same bank read array read status register read cfi query read electronic signature program erase program/ erase suspend program/ erase resume idle yes yes yes yes yes yes yes yes programming C (2) yes yes yes C C yes C erasing C (2) yes yes yes C C yes C program suspended ye s (1) yes yes yes C C C ye s erase suspended ye s (1) yes yes yes yes (1) CCyes
37/92 m36wt864tf, m36wt864bf flash block locking the flash memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. this locking scheme has three levels of protection. lock/unlock - this first level allows software- only control of block locking. lock-down - this second level requires hardware interaction before locking can be changed. v ppf v pplk - the third level offers a complete hardware protection against program and erase on all blocks. the protection status of each block can be set to locked, unlocked, and lock-down. table 13, de- fines all of the possible protection states (wp , dq1, dq0), and appendix c, figure 34, shows a flowchart for the locking operations. reading a blocks lock status the lock status of every block can be read in the read electronic signature mode of the device. to enter this mode write 90h to the device. subse- quent reads at the address specified in table 6, will output the protection status of that block. the lock status is represented by dq0 and dq1. dq0 indicates the block lock/unlock status and is set by the lock command and cleared by the unlock command. it is also automatically set when enter- ing lock-down. dq1 indicates the lock-down sta- tus and is set by the lock-down command. it cannot be cleared by software, only by a hardware reset or power-down. the following sections explain the operation of the locking system. locked state the default status of all blocks on power-up or af- ter a hardware reset is locked (states (0,0,1) or (1,0,1)). locked blocks are fully protected from any program or erase. any program or erase oper- ations attempted on a locked block will return an error in the status register. the status of a locked block can be changed to unlocked or lock-down using the appropriate software com- mands. an unlocked block can be locked by issu- ing the lock command. unlocked state unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. all unlocked blocks return to the locked state after a hardware reset or when the device is powered-down. the status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. a locked block can be un- locked by issuing the unlock command. lock-down state blocks that are locked-down (state (0,1,x))are protected from program and erase operations (as for locked blocks) but their protection status can- not be changed using software commands alone. a locked or unlocked block can be locked-down by issuing the lock-down command. locked- down blocks revert to the locked state when the device is reset or powered-down. the lock-down function is dependent on the wp input pin. when wp =0 (v il ), the blocks in the lock-down state (0,1,x) are protected from pro- gram, erase and protection status changes. when wp =1 (v ih ) the lock-down function is disabled (1,1,x) and locked-down blocks can be individual- ly unlocked to the (1,1,0) state by issuing the soft- ware command, where they can be erased and programmed. these blocks can then be re-locked (1,1,1) and unlocked (1,1,0) as desired while wp remains high. when wp is low , blocks that were previously locked-down return to the lock-down state (0,1,x) regardless of any changes made while wp was high. device reset or power-down resets all blocks , including those in lock-down, to the locked state. locking operations during erase suspend changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. this is useful in the case when another block needs to be updated while an erase operation is in progress. to change block locking during an erase opera- tion, first write the erase suspend command, then check the status register until it indicates that the erase operation has been suspended. next write the desired lock command sequence to a block and the lock status will be changed. after complet- ing any desired lock, read, or program operations, resume the erase operation with the erase re- sume command. if a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. locking operations cannot be performed during a program suspend. refer to appendix , command interface state table, for detailed information on which commands are valid during erase suspend.
m36wt864tf, m36wt864bf 38/92 table 13. flash lock status note: 1. the lock status is defined by the write protect pin and by dq1 (1 for a locked-down block) and dq0 (1 for a locked b lock) as read in the read electronic signature command with a1 = v ih and a0 = v il . 2. all blocks are locked at power-up, so the default configuration is 001 or 101 according to wp status. 3. a wp transition to v ih on a locked block will restore the previous dq0 value, giving a 111 or 110. current protection status (1) (wp , dq1, dq0) next protection status (1) (wp , dq1, dq0) current state program/erase allowed after block lock command after block unlock command after block lock-down command after wp transition 1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0 1,0,1 (2) no 1,0,1 1,0,0 1,1,1 0,0,1 1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0 0,0,1 (2) no 0,0,1 0,0,0 0,1,1 1,0,1 0,1,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,0 (3)
39/92 m36wt864tf, m36wt864bf flash program and erase times and endurance cycles the program and erase times and the number of program/ erase cycles per block are shown in ta- ble 14. in the flash memory the maximum number of program/ erase cycles depends on the voltage supply used. table 14. flash program, erase times and endurance cycles note: 1. t a = C40 to 85c; v dd = 1.65v to 2.2v; v ddq = 1.65v to 3.3v. 2. the difference between preprogrammed and not preprogrammed is not significant (?30ms). 3. excludes the time needed to execute the command sequence. 4. t.b.a. = to be announced parameter condition min typ typical after 100k w/e cycles max unit v ppf = v dd parameter block (4 kword) erase (2) 0.3 1 2.5 s main block (32 kword) erase preprogrammed 0.8 3 4 s not preprogrammed 1.1 4 s bank (4mbit) erase preprogrammed 3 s not preprogrammed 4.5 s parameter block (4 kword) program (3) 40 ms main block (32 kword) program (3) 300 ms word program (3) 10 10 100 s program suspend latency 5 10 s erase suspend latency 5 20 s program/erase cycles (per block) main blocks 100,000 cycles parameter blocks 100,000 cycles v ppf = v pph parameter block (4 kword) erase 0.3 2.5 s main block (32 kword) erase 0.9 4 s bank (4mbit) erase 3.5 s bank (4mbit) program (quad-enhanced factory program) t.b.a. (4) s 4mbit program quadruple word 510 ms word/ double word/ quadruple word program (3) 8 100 s parameter block (4 kword) program (3) quadruple word 8 ms word 32 ms main block (32 kword) program (3) quadruple word 64 ms word 256 ms program/erase cycles (per block) main blocks 1000 cycles parameter blocks 2500 cycles
m36wt864tf, m36wt864bf 40/92 sram operations there are five standard operations that control the sram component. these are bus read, bus write, standby/power-down, data retention and output disable. a summary is shown in table 2, main operation modes read. read operations are used to output the contents of the sram array. the data is output ei- ther by x8 (dq0-dq7) or x16 (dq0-dq15) de- pending on which of the lbs and ubs signals are enabled. the sram is in read mode whenever chip enable, e2s, and write enable, ws , are at v ih , and output enable, gs , and chip enable e1s are at v il . valid data will be available on the output pins after a time of t avqv after the last stable address. if the chip enable or output enable access times are not met, data access will be measured from the limiting parameter (t elqv , t ehqv , or t glqv ) rather than the address. data out may be indeterminate at t elqx , t glqx and t blqx , but data lines will al- ways be valid at t avqv (see table 26, figures 19 and 20). write. write operations are used to write data to the sram. the sram is in write mode whenever write enable, ws , and chip enable, e 1s , are at v il , and chip enable, e2s, is at v ih . either the chip enable input, e1s or the write en- able input, ws , must be deasserted during ad- dress transitions for subsequent write cycles. a write operation is initiated when e1s is at v il , e2s is at v ih and ws is at v il . when ubs or lbs are low, the data is latched on the falling edge of e1s , or w s , whichever occurs first. when ubs or lbs are high, the data is latched on the falling edge of ubs , or lbs , whichever occurs first. the write cycle is terminated on the rising edge of e1s , w s , ubs or lbs , whichever occurs first. if the output is enabled (e1s =v il , e2s=v ih , gs =v il and ubs =lbs =v il ), then ws will return the outputs to high impedance within t wlqz of its falling edge. care must be taken to avoid bus con- tention in this type of operation. the data input must be valid for t dvwh before the rising edge of write enable, for t dveh before the rising edge of e1s or for t dvbh before the rising edge of ubs / lbs , whichever occurs first, and remain valid for t whdx , t ehdx and t bhdx respectively. (see table 27, figure 22, 23 and 24). standby/power-down . the sram component has a chip enabled power-down feature which in- vokes an automatic standby mode (see table 26, figure 19). the sram is in standby mode when- ever either chip enable is deasserted, e1s at v ih or e2s at v il . data retention. the sram data retention per- formances as v dds go down to v dr are described in table 28 and figures 25 and 26. in e1s con- trolled data retention mode, the minimum standby current mode is entered when e1s v dds C0.2v and e2s 0.2v or e2s v dds C 0.2v. in e2s controlled data retention mode, minimum standby current mode is entered when e2s 0.2v. output disable. the sram is in the output dis- able state when gs and ws are both at v ih , refer to table 2 for more details.
41/92 m36wt864tf, m36wt864bf maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 15. absolute maximum ratings value symbol parameter min max unit t a ambient operating temperature C40 85 c t bias temperature under bias C40 125 c t stg storage temperature C65 155 c v io input or output voltage C0.5 v ddqf +0.6 v v ddf supply voltage C0.2 2.45 v v ddqf / v dds input/output supply voltage C0.2 3.3 v v ppf program voltage C0.2 14 v i o output short circuit current 100 ma t vppfh time for v ppf at v ppfh 100 hours
m36wt864tf, m36wt864bf 42/92 dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 16, operating and ac measurement conditions. designers should check that the operating conditions in their circuit match the operating conditions when rely- ing on the quoted parameters. table 16. operating and ac measurement conditions figure 9. ac measurement i/o waveform note: v ddf = v dds figure 10. ac measurement load circuit table 17. device capacitance note: sampled only, not 100% tested. parameter sram flash memory units 70 70/ 85/ 100 min max min max v dd supply voltage C C 1.65 2.2 v v ddq supply voltage 2.7 3.3 2.7 3.3 v v ppf supply voltage (factory environment) 11.4 12.6 v v ppf supply voltage (application environment) -0.4 v ddq +0 .4 v ambient operating temperature C 40 85 C 40 85 c load capacitance (c l ) 30 30 pf input rise and fall times 2 5 ns input pulse voltages 0 to v ddf 0 to v ddq v input and output timing ref. voltages v ddf /2 v ddq /2 v ai06110 v ddf 0v v ddf /2 ai06274 v ddqf c l c l includes jig capacitance 16.7k device under test 0.1f v ddf 0.1f v ddqf 16.7k symbol parameter test condition min max unit c in input capacitance v in = 0v 68pf c out output capacitance v out = 0v 812pf
43/92 m36wt864tf, m36wt864bf table 18. flash dc characteristics - currents note: 1. sampled only, not 100% tested. 2. v dd dual operation current is the sum of read and program or erase currents. symbol parameter test condition min typ max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 1 a i dd1 supply current asynchronous read (f=6mhz) e = v il , g = v ih 36ma supply current synchronous read (f=40mhz) 4 word 6 13 ma 8 word 8 14 ma continuous 6 10 ma supply current synchronous read (f=54mhz) 4 word 7 16 ma 8 word 10 18 ma continuous 13 25 ma i dd2 supply current (reset) rp = v ss 0.2v 10 50 a i dd3 supply current (standby) e = v dd 0.2v 10 50 a i dd4 supply current (automatic standby) e = v il , g = v ih 10 50 a i dd5 (1) supply current (program) v ppf = v pph 815ma v ppf = v dd 10 20 ma supply current (erase) v ppf = v pph 815ma v ppf = v dd 10 20 ma i dd6 (1,2) supply current (dual operations) program/erase in one bank, asynchronous read in another bank 13 26 ma program/erase in one bank, synchronous read in another bank 16 30 ma i dd7 (1) supply current program/ erase suspended (standby) e = v dd 0.2v 10 50 a i pp1 (1) v ppf supply current (program) v ppf = v pph 25ma v ppf = v dd 0.2 5 a v ppf supply current (erase) v ppf = v pph 25ma v ppf = v dd 0.2 5 a i pp2 v ppf supply current (read) v ppf = v pph 100 400 a v ppf v dd 0.2 5 a i pp3 (1) v ppf supply current (standby) v ppf v dd 0.2 5 a
m36wt864tf, m36wt864bf 44/92 table 19. flash dc characteristics - voltages table 20. sram dc characteristics note: 1. average ac current, cycling at t avav minimum. 2. e1 = v il and e2 = v ih, lb or/and ub = v il , v in = v il or v ih . 3. e1 0.2v and e2 v dds C0.2v, lb or/and ub 0.2v, v in 0.2v or v in v dds C0.2v. 4. output disabled. symbol parameter test condition min typ max unit v il input low voltage C0.5 0.4 v v ih input high voltage v ddq C0.4 v ddq + 0.4 v v ol output low voltage i ol = 100a 0.1 v v oh output high voltage i oh = C100a v ddq C0.1 v v pp1 v ppf program voltage-logic program, erase 1 1.8 1.95 v v pph v ppf program voltage factory program, erase 11.4 12 12.6 v v pplk program or erase lockout 0.9 v v lko v dd lock voltage 1v v rph rp pin extended high voltage 3.3 v symbol parameter test condition min typ max unit i dd1 (1,2) operating supply current v dds = 3.3v, f = 1/t avav , i out = 0ma 70ns 35 ma i dd2 (3) operating supply current v dds = 3.3v, f = 1mhz, i out = 0ma 4ma i sb standby supply current cmos v dds = 3.3v, f = 0, e1 v dds C0.2v or e2 0.2v or lb =ub v dds C0.2v 120a i li input leakage current 0v v in v dds C1 1 a i lo output leakage current 0v v out v dds (4) C1 1 a v ih input high voltage 2.2 v dds + 0.3 v v il input low voltage C0.3 0.6 v v oh output high voltage i oh = C1.0ma 2.4 v v ol output low voltage i ol = 2.1ma 0.4 v
45/92 m36wt864tf, m36wt864bf figure 11. flash asynchronous random access read ac waveforms ai06275 tavav tavqv telqx tehqx tglqv tglqx tghqx dq0-dq15 ef gf telqv tehqz tghqz valid a0-a21 valid valid lf tellh tllqv tlllh tavlh tlhax taxqx waitf teltv tehtz note. write enable, wf, is high, wait is active low. valid address latch outputs enabled data valid standby tlhgl hi-z hi-z
m36wt864tf, m36wt864bf 46/92 figure 12. flash asynchronous page read ac waveforms ai06276 a2-a21 ef gf a0-a1 valid address lf dq0-dq15 valid address valid address valid address valid address valid data valid data valid data valid data tlhax tavlh tllqv tavqv1 tglqx tlllh tellh waitf tavav telqv telqx teltv tglqv (1) note 1. wait is active low. valid address latch outputs enabled valid data standby tlhgl hi-z
47/92 m36wt864tf, m36wt864bf table 21. flash asynchronous read ac characteristics note: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv - t glqv after the falling edge of e without increasing t elqv . 3. to be characterized. symbol alt parameter m36wt864tf/bf unit 70 85 100 read timings t avav t rc address valid to next address valid min 70 (3) 85 100 ns t avqv t acc address valid to output valid (random) max 70 (3) 85 100 ns t avqv1 t page address valid to output valid (page) max 20 (3) 25 25 ns t axqx (1) t oh address transition to output transition min 0 0 0 ns t eltv chip enable low to wait valid max 14 (3) 18 18 ns t elqv (2) t ce chip enable low to output valid max 70 (3) 85 100 ns t elqx (1) t lz chip enable low to output transition min 0 0 0 ns t ehtz chip enable high to wait hi-z max 20 (3) 20 20 ns t ehqx (1) t oh chip enable high to output transition min 0 0 0 ns t ehqz (1) t hz chip enable high to output hi-z max 20 (3) 20 20 ns t glqv (2) t oe output enable low to output valid max 20 25 25 ns t glqx (1) t olz output enable low to output transition min 0 0 0 ns t ghqx (1) t oh output enable high to output transition min 0 0 0 ns t ghqz (1) t df output enable high to output hi-z max 20 (3) 20 20 ns latch timings t av lh t avadvh address valid to latch enable high min 10 10 10 ns t ellh t eladvh chip enable low to latch enable high min 10 10 10 ns t lhax t advhax latch enable high to address transition min 10 10 10 ns t lllh t advladvh latch enable pulse width min 10 10 10 ns t llqv t advlqv latch enable low to output valid (random) max 70 (3) 85 100 ns t lhgl t advhgl latch enable high to output enable low min 0 0 0 ns
m36wt864tf, m36wt864bf 48/92 figure 13. flash synchronous burst read ac waveforms ai06277 dq0-dq15 ef gf a0-a21 lf waitf kf valid valid valid address tlllh tavlh tglqx tavkh tllkh telkh tkhax tkhqx tkhqv not valid valid note 1 note 2 note 2 tkhtx tkhtv tehqx tehqz tghqx tghqz tkhtx hi-z valid note 2 teltv tkhtv tehtz address latch x latency valid data flow boundary crossing valid data standby note 1. the number of clock cycles to be inserted depends on the x latency set in the configuration register. 2. the wait signal can be configured to be active during wait state or one cycle before. wait signal is active low. 3. address latched and data output on the rising clock edge. tehel tkhqv tkhqx tkhqv tkhqx hi-z
49/92 m36wt864tf, m36wt864bf figure 14. flash single synchronous read ac waveforms ai06278 dq0-dq15 ef gf a0-a21 lf waitf (2) kf (4) valid not valid valid address tlllh tavlh tglqv tavkh tllkh telkh tkhax not valid not valid note 1 tehqx tehqz tghqx tghqz hi-z not valid note 3 teltv tkhqv tehtz note 1. the number of clock cycles to be inserted depends on the x latency set in the configuration register. 2. the wait signal is configured to be active during wait state. wait signal is active low. 3. wait is always asserted when addressed bank is in read cfi, read sr or read electronic signature mode. wait signals valid data if the addressed bank is in read array mode. 4. address latched and data output on the rising clock edge. not valid tglqx tehel tkhtv hi-z
m36wt864tf, m36wt864bf 50/92 figure 15. flash clock input ac waveform table 22. flash synchronous read ac characteristics note: 1. sampled only, not 100% tested. 2. for other timings please refer to table 21, asynchronous read ac characteristics. 3. to be characterized. symbol alt parameter m36wt864tf/bf unit 70 85 100 synchronous read timings t avkh t av clkh address valid to clock high min 9 9 9 ns t elkh t elclkh chip enable low to clock high min 9 9 9 ns t eltv chip enable low to wait valid max 14 (3) 18 18 ns t ehel chip enable pulse width (subsequent synchronous reads) min 14 (3) 14 14 ns t ehtz chip enable high to wait hi-z max 20 (3) 20 20 ns t khax t clkhax clock high to address transition min 10 10 10 ns t khqv t khtv t clkhqv clock high to output valid clock high to wait valid max 14 (3) 18 18 ns t khqx t khtx t clkhqx clock high to output transition clock high to wait transition min 4 4 4 ns t llkh t advlclkh latch enable low to clock high min 9 9 9 ns clock specifications t khkh t clk clock period (f=40mhz) min 25 25 ns clock period (f=54mhz) min 18.5 ns t khkl t klkh clock high to clock low clock low to clock high min 4.5 5 5 ns t f t r clock fall or rise time max 3 3 3 ns ai06981 tkhkh tf tr tkhkl tklkh
51/92 m36wt864tf, m36wt864bf figure 16. flash write ac waveforms, write enable controlled ef gf wf dq0-dq15 command cmd or data status register v ppf valid address a0-a21 tavav tqvvpl tavwh twhax program or erase telwl twheh twhdx tdvwh twlwh twhwl tvphwh set-up command confirm command or data input status register read 1st polling telqv ai06279 twphwh wpf twhgl tqvwpl twhel bank address valid address lf tavlh tlllh tellh tlhax tghwl twhqv twhwpl twhvpl telkv kf twhll twhav
m36wt864tf, m36wt864bf 52/92 table 23. flash write ac characteristics, write enable controlled note: 1. sampled only, not 100% tested. 2. t whel has the values shown when reading in the targeted bank. system designers should take this into account and may insert a software no-op instruction to delay the first read in the same bank after issuing a command. if it is a read array operation in a different bank t whel is 0ns. 3. to be characterized. 4. meaningful only if lf is always kept low. symbol alt parameter m36wt864tf/bf unit 70 85 100 write enable controlled timings t avav t wc address valid to next address valid min 70 (3) 85 100 ns t avl h address valid to latch enable high min 10 10 10 ns t avwh (4) t wc address valid to write enable high min 45 (3) 50 50 ns t dvwh t ds data valid to write enable high min 45 (3) 50 50 ns t ellh chip enable low to latch enable high min 10 10 10 ns t elwl t cs chip enable low to write enable low min 0 0 0 ns t elqv chip enable low to output valid min 70 (3) 85 100 ns t elkv chip enable high to clock valid min 9 9 9 ns t ghwl output enable high to write enable low min 20 20 20 ns t lhax latch enable high to address transition min 10 10 10 ns t lllh latch enable pulse width min 10 10 10 ns t whav (4) write enable high to address valid min 0 0 0 ns t whax (4) t ah write enable high to address transition min 0 0 0 ns t whdx t dh write enable high to input transition min 0 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 0 ns t whel (2) write enable high to chip enable low min 25 (3) 25 25 ns t whgl write enable high to output enable low min 0 0 0 ns t whll write enable high to latch enable low min 0 0 0 ns t whwl t wph write enable high to write enable low min 25 25 25 ns t whqv write enable high to output valid min 95 (3) 110 125 ns t wlwh t wp write enable low to write enable high min 45 (3) 50 50 ns protection timings t qvvpl output (status register) valid to v ppf low min 0 0 0 ns t qvwpl output (status register) valid to write protect low min 0 0 0 ns t vphwh t vps v ppf high to write enable high min 200 200 200 ns t whvpl write enable high to v ppf low min 200 200 200 ns t whwpl write enable high to write protect low min 200 200 200 ns t wphwh write protect high to write enable high min 200 200 200 ns
53/92 m36wt864tf, m36wt864bf figure 17. flash write ac waveforms, chip enable controlled wf gf ef dq0-dq15 command cmd or data status register v ppf valid address a0-a21 tavav tqvvpl taveh tehax program or erase twlel tehwh tehdx tdveh teleh tehel tvpheh set-up command confirm command or data input status register read 1st polling telqv ai06280 twpheh wpf tehgl tqvwpl twhel bank address valid address lf tavlh tlllh tlhax tghel tehwpl tehvpl telkv kf tellh twhqv
m36wt864tf, m36wt864bf 54/92 table 24. flash write ac characteristics, chip enable controlled note: 1. sampled only, not 100% tested. 2. t whel has the values shown when reading in the targeted bank. system designers should take this into account and may insert a software no-op instruction to delay the first read in the same bank after issuing a command. if it is a read array operation in a different bank t whel is 0ns. 3. to be characterized. symbol alt parameter m36wt864tf/bf unit 70 85 100 chip enable controlled timings t avav t wc address valid to next address valid min 70 (3) 85 100 ns t ave h t wc address valid to chip enable high min 45 (3) 50 50 ns t avlh address valid to latch enable high min 10 10 10 ns t dveh t ds data valid to write enable high min 45 (3) 50 50 ns t ehax t ah chip enable high to address transition min 0 0 0 ns t ehdx t dh chip enable high to input transition min 0 0 0 ns t ehel t wph chip enable high to chip enable low min 25 25 25 ns t ehgl chip enable high to output enable low min 0 0 0 ns t ehwh t ch chip enable high to write enable high min 0 0 0 ns t elkv chip enable low to clock valid min 9 9 9 ns t eleh t wp chip enable low to chip enable high min 45 (3) 50 50 ns t ellh chip enable low to latch enable high min 10 10 10 ns t elqv chip enable low to output valid min 70 (3) 85 100 ns t ghel output enable high to chip enable low min 20 20 20 ns t lhax latch enable high to address transition min 10 10 10 ns t lllh latch enable pulse width min 10 10 10 ns t whel (2) write enable high to chip enable low min 25 (3) 25 25 ns t whqv write enable high to output valid min 95 110 125 ns t wlel t cs write enable low to chip enable low min 0 0 0 ns protection timings t ehvpl chip enable high to v ppf low min 200 200 200 ns t ehwpl chip enable high to write protect low min 200 200 200 ns t qvvpl output (status register) valid to v ppf low min 0 0 0 ns t qvwpl output (status register) valid to write protect low min 0 0 0 ns t vpheh t vps v ppf high to chip enable high min 200 200 200 ns t wpheh write protect high to chip enable high min 200 200 200 ns
55/92 m36wt864tf, m36wt864bf figure 18. flash reset and power-up ac waveforms table 25. flash reset and power-up ac characteristics note: 1. the device reset is possible but not guaranteed if t plph < 50ns. 2. sampled only, not 100% tested. 3. it is important to assert rp in order to allow proper cpu initialization during power-up or reset. symbol parameter test condition 70 85 100 unit t plwl t plel t plgl t plll reset low to write enable low, chip enable low, output enable low, latch enable low during program min 10 10 10 s during erase min 20 20 20 s other conditions min 80 80 80 ns t phwl t phel t phgl t phll reset high to write enable low chip enable low output enable low latch enable low min 30 30 30 ns t plph (1,2) rp pulse width min 50 50 50 ns t vdhph (3) supply voltages high to reset high min 50 50 50 s ai06281 wf, ef, gf, lf rp vdd, vddq tvdhph tplph power-up reset tplwl tplel tplgl tplll tphwl tphel tphgl tphll
m36wt864tf, m36wt864bf 56/92 figure 19. sram address controlled, read ac waveforms note: e1s = low, e2s = high, gs = low, ws = high, ubs = low and/or lbs = low. figure 20. sram chip enable or output enable controlled, read ac waveforms note: write enable (wf ) = high ai05839 tavav tavqv taxqx a0-a18 dq0-dq7 and/or dq8-dq15 valid data valid ai06282 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a18 e1s gs dq0-dq15 valid tblqv tblqx tbhqz ubs, lbs e2s
57/92 m36wt864tf, m36wt864bf figure 21. sram chip enable or ubs /lbs controlled, standby ac waveforms table 26. sram read and standby ac characteristics note: 1. test conditions assume transition timing reference level = 0.3v dds or 0.7v dds . 2. at any given temperature and voltage condition, t ghqz is less than t glqx , t bhqz is less than t blqx and t ehqz is less than t elqx for any given device. 3. these parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to o utput voltage levels. 4. tested initially and after any design or process changes that may affect these parameters. symbol parameter m36wt864tf/bf unit 70 t avav read cycle time min 70 ns t avqv address valid to output valid max 70 ns t axqx (1) data hold from address change min 5 ns t bhqz (2,3,4) upper/lower byte enable high to output hi-z max 25 ns t blqv upper/lower byte enable low to output valid max 70 ns t blqx (1) upper/lower byte enable low to output transition min 5 ns t ehqz (2,3,4) chip enable high to output hi-z max 25 ns t elqv chip enable low to output valid max 70 ns t elqx (1) chip enable low to output transition min 5 ns t ghqz (2,3,4) output enable high to output hi-z max 25 ns t glqv output enable low to output valid max 35 ns t glqx (1) output enable low to output transition min 5 ns t pd (4) chip enable or ub /lb high to power down max 0 ns t pu (4) chip enable or ub /lb low to power up min 70 ns ai06283 tpd i dd tpu i sb 50% e1s, ubs, lbs e2s
m36wt864tf, m36wt864bf 58/92 figure 22. sram write ac waveforms, write enable controlled note: 1. during this period dq0-dq15 are in output state and input signals should not be applied. ai06284 tavav twhax tdvwh data input a0-a18 e1s ws dq0-dq15 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx tblbh ubs, lbs e2s telwh
59/92 m36wt864tf, m36wt864bf figure 23. sram write ac waveforms, chip enable controlled figure 24. sram write ac waveforms, ub /lb controlled note: 1. during this period dq0-dq15 are in output state and input signals should not be applied. ai06285 tavav tehax tdveh a0-a18 e1s ws dq0-dq15 valid taveh tavel tavwl teleh tehdx data input tblbh ubs, lbs e2s twleh ai06286 tavav tbhax tdvbh data input a0-a18 e1s ws dq0-dq15 valid tavbh tavwl twlqz tbhdx tblbh ubs, lbs data (1) tavbl e2s twlbh
m36wt864tf, m36wt864bf 60/92 table 27. sram write ac characteristics note: 1. at any given temperature and voltage condition, t wlqz is less than t whqx for any given device. 2. these parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to o utput voltage levels. 3. tested initially and after any design or process changes that may affect these parameters. symbol parameter m36wt864tf/bf unit 70 t avav write cycle time min 70 ns t av bh address valid to lbs , ubs high min 60 ns t avbl address valid to lbs , ubs low min 0 ns t av eh address valid to chip enable high min 60 ns t avel address valid to chip enable low min 0 ns t av wh address valid to write enable high min 60 ns t avwl address valid to write enable low min 0 ns t bhax lbs , ubs high to address transition min 0 ns t bhdx lbs , ubs high to input transition min 0 ns t blbh lbs , ubs low to lbs , ubs high min 60 ns t bleh lbs , ubs low to chip enable high min 60 ns t blwh lbs , ubs low to write enable high min 60 ns t dvbh input valid to lbs , ubs high min 30 ns t dveh input valid to chip enable high min 30 ns t dvwh input valid to write enable high min 30 ns t ehax chip enable high to address transition min 0 ns t ehdx chip enable high to input transition min 0 ns t elbh chip enable low to lbs , ubs high min 60 ns t eleh chip enable low to chip enable high min 60 ns t elwh chip enable low to write enable high min 60 ns t whax write enable high to address transition min 0 ns t whdx write enable high to input transition min 0 ns t whqx (1) write enable high to output transition min 5 ns t wlbh write enable low to lbs , ubs high min 60 ns t wleh write enable low to chip enable high min 60 ns t wlqz (1,2,3) write enable low to output hi-z max 20 ns t wlwh write enable low to write enable high min 50 ns
61/92 m36wt864tf, m36wt864bf figure 25. sram low v dd data retention ac waveforms, e1s controlled figure 26. sram low v dd data retention ac waveforms, e2s controlled table 28. sram low v dd data retention characteristics note: 1. all other inputs at v ih v dds C0.2v or v il 0.2v. 2. tested initially and after any design or process that may affect these parameters. t avav is read cycle time. 3. no input may exceed v dds +0.2v. symbol parameter test condition min typ max unit i dddr (1) supply current (data retention) v dd = 1.5v, e1s v dds C0.2v or e2s 0.2v or ubs = lbs v dds C0.2v, f = 0 510a t cdr (1,2) chip deselected to data retention time 0ns t r (2) operation recovery time t avav ns v dr (1) supply voltage (data retention) e1s v dds C0.2v or e2s 0.2v or ubs = lbs v dds C0.2v, f = 0 1.5 v ai06287 data retention mode tr 3.3v tcdr v dds 2.7v v dr > 1.5v e1s or ubs/lbs e1s v dr C 0.2v or ubs = lbs v dr C 0.2v ai06288 data retention mode tr 3.3v tcdr v dds 2.7v v dr > 1.5v e2s e2s 0.2v
m36wt864tf, m36wt864bf 62/92 package mechanical figure 27. stacked lfbga96 - 8x14mm, 8x10ball array, 0.8mm pitch, bottom view package outline note: drawing is not to scale. table 29. stacked lfbga96 - 8x14mm, 8x10 ball array, 0.8mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.400 0.0551 a1 0.300 0.0118 a2 0.960 0.0378 b 0.400 0.350 0.450 0.0157 0.0138 0.0177 d 8.000 7.900 8.100 0.3150 0.3110 0.3189 d1 5.600 C C 0.2205 C C ddd 0.100 0.0039 e 14.000 13.900 14.100 0.5512 0.5472 0.5551 e1 7.200 C C 0.2835 C C e2 10.400 C C 0.4094 C C e 0.800 C C 0.0315 C C fd 1.200 C C 0.0472 C C fe 3.400 C C 0.1339 C C fe1 1.800 C C 0.0709 C C sd 0.400 C C 0.0157 C C se 0.400 C C 0.0157 C C a2 a1 a bga-z31 ddd d e e b se fd fe1 e2 d1 sd ball "a1" e1 fe
63/92 m36wt864tf, m36wt864bf part numbering table 30. ordering information scheme devices are shipped from the factory with the memory content bits erased to 1. for a list of available op- tions (speed, package, etc...) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. example: m36wt864tf 70 za 6 t device type m36 = mmp (flash + sram) architecture w = multiple bank, burst mode operating voltage t = v ddf = 1.65v to 2.2v; v dds = v ddqf = 2.7v to 3.3v sram chip size & organization 8 = 8 mbit (512k x16-bit) device function 64t = 64 mbit (x16), multiple bank, top boot 64b = 64 mbit (x16), multiple bank, bottom boot b = sram asynchronous 70ns speed 70 = 70ns 85 = 85ns 10 = 100ns package za = lfbga96 - 8x14mm, 8x10 ball array, 0.8mm pitch temperature range 6 = C40 to 85c option t = tape & reel packing
m36wt864tf, m36wt864bf 64/92 revision history table 31. document revision history date version revision details 10-jul-2002 1.0 first issue
65/92 m36wt864tf, m36wt864bf appendix a. flash block address tables table 32. flash top boot block addresses bank # size (kword) address range parameter bank 0 4 3ff000-3fffff 1 4 3fe000-3fefff 2 4 3fd000-3fdfff 3 4 3fc000-3fcfff 4 4 3fb000-3fbfff 5 4 3fa000-3fafff 6 4 3f9000-3f9fff 7 4 3f8000-3f8fff 8 32 3f0000-3f7fff 9 32 3e8000-3effff 10 32 3e0000-3e7fff 11 32 3d8000-3dffff 12 32 3d0000-3d7fff 13 32 3c8000-3cffff 14 32 3c0000-3c7fff bank 0 15 32 3b8000-3bffff 16 32 3b0000-3b7fff 17 32 3a8000-3affff 18 32 3a0000-3a7fff 19 32 398000-39ffff 20 32 390000-397fff 21 32 388000-38ffff 22 32 380000-387fff bank 1 23 32 378000-37ffff 24 32 370000-377fff 25 32 368000-36ffff 26 32 360000-367fff 27 32 358000-35ffff 28 32 350000-357fff 29 32 348000-34ffff 30 32 340000-347fff bank 2 31 32 338000-33ffff 32 32 330000-337fff 33 32 328000-32ffff 34 32 320000-327fff 35 32 318000-31ffff 36 32 310000-317fff 37 32 308000-30ffff 38 32 300000-307fff bank 3 39 32 2f8000-2fffff 40 32 2f0000-2f7fff 41 32 2e8000-2effff 42 32 2e0000-2e7fff 43 32 2d8000-2dffff 44 32 2d0000-2d7fff 45 32 2c8000-2cffff 46 32 2c0000-2c7fff bank 4 47 32 2b8000-2bffff 48 32 2b0000-2b7fff 49 32 2a8000-2affff 50 32 2a0000-2a7fff 51 32 298000-29ffff 52 32 290000-297fff 53 32 288000-28ffff 54 32 280000-287fff bank 5 55 32 278000-27ffff 56 32 270000-277fff 57 32 268000-26ffff 58 32 260000-267fff 59 32 258000-25ffff 60 32 250000-257fff 61 32 248000-24ffff 62 32 240000-247fff bank 6 63 32 238000-23ffff 64 32 230000-237fff 65 32 228000-22ffff 66 32 220000-227fff 67 32 218000-21ffff 68 32 210000-217fff 69 32 208000-20ffff 70 32 200000-207fff bank 7 71 32 1f8000-1fffff 72 32 1f0000-1f7fff 73 32 1e8000-1effff 74 32 1e0000-1e7fff 75 32 1d8000-1dffff 76 32 1d0000-1d7fff 77 32 1c8000-1cffff 78 32 1c0000-1c7fff
m36wt864tf, m36wt864bf 66/92 note: there are two bank regions, region 1 contains all the banks that are made up of main blocks only, region 2 contains the banks that are made up of the parameter and main blocks. bank 8 79 32 1b8000-1bffff 80 32 1b0000-1b7fff 81 32 1a8000-1affff 82 32 1a0000-1a7fff 83 32 198000-19ffff 84 32 190000-197fff 85 32 188000-18ffff 86 32 180000-187fff bank 9 87 32 178000-17ffff 88 32 170000-177fff 89 32 168000-16ffff 90 32 160000-167fff 91 32 158000-15ffff 92 32 150000-157fff 93 32 148000-14ffff 94 32 140000-147fff bank 10 95 32 138000-13ffff 96 32 130000-137fff 97 32 128000-12ffff 98 32 120000-127fff 99 32 118000-11ffff 100 32 110000-117fff 101 32 108000-10ffff 102 32 100000-107fff bank 11 103 32 0f8000-0fffff 104 32 0f0000-0f7fff 105 32 0e8000-0effff 106 32 0e0000-0e7fff 107 32 0d8000-0dffff 108 32 0d0000-0d7fff 109 32 0c8000-0cffff 110 32 0c0000-0c7fff bank 12 111 32 0b8000-0bffff 112 32 0b0000-0b7fff 113 32 0a8000-0affff 114 32 0a0000-0a7fff 115 32 098000-09ffff 116 32 090000-097fff 117 32 088000-08ffff 118 32 080000-087fff bank 13 119 32 078000-07ffff 120 32 070000-077fff 121 32 068000-06ffff 122 32 060000-067fff 123 32 058000-05ffff 124 32 050000-057fff 125 32 048000-04ffff 126 32 040000-047fff bank 14 127 32 038000-03ffff 128 32 030000-037fff 129 32 028000-02ffff 130 32 020000-027fff 131 32 018000-01ffff 132 32 010000-017fff 133 32 008000-00ffff 134 32 000000-007fff
67/92 m36wt864tf, m36wt864bf table 33. flash bottom boot block addresses bank # size (kword) address range bank 14 134 32 3f8000-3fffff 133 32 3f0000-3f7fff 132 32 3e8000-3effff 131 32 3e0000-3e7fff 130 32 3d8000-3dffff 129 32 3d0000-3d7fff 128 32 3c8000-3cffff 127 32 3c0000-3c7fff bank 13 126 32 3b8000-3bffff 125 32 3b0000-3b7fff 124 32 3a8000-3affff 123 32 3a0000-3a7fff 122 32 398000-39ffff 121 32 390000-397fff 120 32 388000-38ffff 119 32 380000-387fff bank 12 118 32 378000-37ffff 117 32 370000-377fff 116 32 368000-36ffff 115 32 360000-367fff 114 32 358000-35ffff 113 32 350000-357fff 112 32 348000-34ffff 111 32 340000-347fff bank 11 110 32 338000-33ffff 109 32 330000-337fff 108 32 328000-32ffff 107 32 320000-327fff 106 32 318000-31ffff 105 32 310000-317fff 104 32 308000-30ffff 103 32 300000-307fff bank 10 102 32 2f8000-2fffff 101 32 2f0000-2f7fff 100 32 2e8000-2effff 99 32 2e0000-2e7fff 98 32 2d8000-2dffff 97 32 2d0000-2d7fff 96 32 2c8000-2cffff 95 32 2c0000-2c7fff bank 9 94 32 2b8000-2bffff 93 32 2b0000-2b7fff 92 32 2a8000-2affff 91 32 2a0000-2a7fff 90 32 298000-29ffff 89 32 290000-297fff 88 32 288000-28ffff 87 32 280000-287fff bank 8 86 32 278000-27ffff 85 32 270000-277fff 84 32 268000-26ffff 83 32 260000-267fff 82 32 258000-25ffff 81 32 250000-257fff 80 32 248000-24ffff 79 32 240000-247fff bank 7 78 32 238000-23ffff 77 32 230000-237fff 76 32 228000-22ffff 75 32 220000-227fff 74 32 218000-21ffff 73 32 210000-217fff 72 32 208000-20ffff 71 32 200000-207fff bank 6 70 32 1f8000-1fffff 69 32 1f0000-1f7fff 68 32 1e8000-1effff 67 32 1e0000-1e7fff 66 32 1d8000-1dffff 65 32 1d0000-1d7fff 64 32 1c8000-1cffff 63 32 1c0000-1c7fff bank 5 62 32 1b8000-1bffff 61 32 1b0000-1b7fff 60 32 1a8000-1affff 59 32 1a0000-1a7fff 58 32 198000-19ffff 57 32 190000-197fff 56 32 188000-18ffff 55 32 180000-187fff
m36wt864tf, m36wt864bf 68/92 note: there are two bank regions, region 1 contains all the banks that are made up of main blocks only, region 2 contains the banks that are made up of the parameter and main blocks. bank 4 54 32 178000-17ffff 53 32 170000-177fff 52 32 168000-16ffff 51 32 160000-167fff 50 32 158000-15ffff 49 32 150000-157fff 48 32 148000-14ffff 47 32 140000-147fff bank 3 46 32 138000-13ffff 45 32 130000-137fff 44 32 128000-12ffff 43 32 120000-127fff 42 32 118000-11ffff 41 32 110000-117fff 40 32 108000-10ffff 39 32 100000-107fff bank 2 38 32 0f8000-0fffff 37 32 0f0000-0f7fff 36 32 0e8000-0effff 35 32 0e0000-0e7fff 34 32 0d8000-0dffff 33 32 0d0000-0d7fff 32 32 0c8000-0cffff 31 32 0c0000-0c7fff bank 1 30 32 0b8000-0bffff 29 32 0b0000-0b7fff 28 32 0a8000-0affff 27 32 0a0000-0a7fff 26 32 098000-09ffff 25 32 090000-097fff 24 32 088000-08ffff 23 32 080000-087fff bank 0 22 32 078000-07ffff 21 32 070000-077fff 20 32 068000-06ffff 19 32 060000-067fff 18 32 058000-05ffff 17 32 050000-057fff 16 32 048000-04ffff 15 32 040000-047fff parameter bank 14 32 038000-03ffff 13 32 030000-037fff 12 32 028000-02ffff 11 32 020000-027fff 10 32 018000-01ffff 9 32 010000-017fff 8 32 008000-00ffff 7 4 007000-007fff 6 4 006000-006fff 5 4 005000-005fff 4 4 004000-004fff 3 4 003000-003fff 2 4 002000-002fff 1 4 001000-001fff 0 4 000000-000fff
69/92 m36wt864tf, m36wt864bf appendix b. flash common flash interface the common flash interface is a jedec ap- proved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the read cfi query command is issued the device enters cfi query mode and the data structure is read from the memory. tables 34, 35, 36, 37, 38, 40 and 1 show the addresses used to retrieve the data. the query data is always pre- sented on the lowest order data outputs (dq0- dq7), the other outputs (dq8-dq15) are set to 0. the cfi data structure also contains a security area where a 64 bit unique security number is writ- ten (see table 1, security code area). this area can be accessed only in read mode by the final user. it is impossible to change the security num- ber after it has been written by st. issue a read array command to return to read mode. table 34. query structure overview note: the flash memory display the cfi data structure when cfi query command is issued. in this table are listed the main sub-se ctions detailed in tables 35, 36, 37, 38, 40 and 1. query data is always presented on the lowest order data outputs. table 35. cfi query identification string offset sub-section name description 00h reserved reserved for algorithm-specific information 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) 80h security code area lock protection register unique device number and user programmable otp offset sub-section name description value 00h 0020h manufacturer code st 01h 8810h 8811h device code top bottom 02h reserved reserved 03h reserved reserved 04h-0fh reserved reserved 10h 0051h query unique ascii string "qry" "q" 11h 0052h "r" 12h 0059h "y" 13h 0003h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm 14h 0000h 15h offset = p = 0039h address for primary algorithm extended query table (see table 37) p = 39h 16h 0000h 17h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 18h 0000h 19h value = a = 0000h address for alternate algorithm extended query table na 1ah 0000h
m36wt864tf, m36wt864bf 70/92 table 36. cfi query system interface information table 37. device geometry definition offset data description value 1bh 0017h v dd logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 1.7v 1ch 0022h v dd logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 2.2v 1dh 0017h v ppf [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 1.7v 1eh 00c0h v ppf [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 12v 1fh 0004h typical time-out per single byte/word program = 2 n s 16s 20h 0003h typical time-out for quadruple word program = 2 n s 8s 21h 000ah typical time-out per individual block erase = 2 n ms 1s 22h 0000h typical time-out for full chip erase = 2 n ms na 23h 0003h maximum time-out for word program = 2 n times typical 128s 24h 0004h maximum time-out for quadruple word = 2 n times typical 128s 25h 0002h maximum time-out per individual block erase = 2 n times typical 4s 26h 0000h maximum time-out for chip erase = 2 n times typical na offset word mode data description value 27h 0017h device size = 2 n in number of bytes 8 mbyte 28h 29h 0001h 0000h flash device interface code description x16 async. 2ah 2bh 0003h 0000h maximum number of bytes in multi-byte program or page = 2 n 8 byte 2ch 0002h number of identical sized erase block regions within the device bit 7 to 0 = x = number of erase block regions 2 m36wt864tf 2dh 2eh 007eh 0000h region 1 information number of identical-size erase blocks = 007eh+1 127 2fh 30h 0000h 0001h region 1 information block size in region 1 = 0100h * 256 byte 64 kbyte 31h 32h 0007h 0000h region 2 information number of identical-size erase blocks = 0007h+1 8 33h 34h 0020h 0000h region 2 information block size in region 2 = 0020h * 256 byte 8 kbyte 35h 38h 0000h reserved for future erase block region information na
71/92 m36wt864tf, m36wt864bf table 38. primary algorithm-specific extended query table m36wt864bf 2dh 2eh 0007h 0000h region 1 information number of identical-size erase block = 0007h+1 8 2fh 30h 0020h 0000h region 1 information block size in region 1 = 0020h * 256 byte 8 kbyte 31h 32h 007eh 0000h region 2 information number of identical-size erase block = 007eh+1 127 33h 34h 0000h 0001h region 2 information block size in region 2 = 0100h * 256 byte 64 kbyte 35h 38h 0000h reserved for future erase block region information na offset data description value (p)h = 39h 0050h primary algorithm extended query table unique ascii string pri "p" 0052h "r" 0049h "i" (p+3)h = 3ch 0031h major version number, ascii "1" (p+4)h = 3dh 0030h minor version number, ascii "0" (p+5)h = 3eh 00e6h extended query table contents for primary algorithm. address (p+5)h contains less significant byte. bit 0 chip erase supported (1 = yes, 0 = no) bit 1 erase suspend supported (1 = yes, 0 = no) bit 2 program suspend supported (1 = yes, 0 = no) bit 3 legacy lock/unlock supported (1 = yes, 0 = no) bit 4 queued erase supported (1 = yes, 0 = no) bit 5 instant individual block locking supported (1 = yes, 0 = no) bit 6 protection bits supported (1 = yes, 0 = no) bit 7 page mode read supported (1 = yes, 0 = no) bit 8 synchronous read supported (1 = yes, 0 = no) bit 9 simultaneous operation supported (1 = yes, 0 = no) bit 10 to 31 reserved; undefined bits are 0. if bit 31 is 1 then another 31 bit field of optional features follows at the end of the bit-30 field. no yes yes no no yes yes yes yes yes 0003h (p+7)h = 40h 0000h (p+8)h = 41h 0000h (p+9)h = 42h 0001h supported functions after suspend read array, read status register and cfi query bit 0 program supported after erase suspend (1 = yes, 0 = no) bit 7 to 1 reserved; undefined bits are 0 yes (p+a)h = 43h 0003h block protect status defines which bits in the block status register section of the query are implemented. bit 0 block protect status register lock/unlock bit active (1 = yes, 0 = no) bit 1 block lock status register lock-down bit active (1 = yes, 0 = no) bit 15 to 2 reserved for future use; undefined bits are 0 yes yes (p+b)h = 44h 0000h offset word mode data description value
m36wt864tf, m36wt864bf 72/92 table 39. protection register information table 40. burst read information table 41. bank and erase block region information note: 1. the variable p is a pointer which is defined at cfi offset 15h. 2. bank regions. there are two bank regions, 1 contains all the banks that are made up of main blocks only, 2 contains the banks that are made up of the parameter and main blocks. (p+c)h = 45h 0018h v dd logic supply optimum program/erase voltage (highest performance) bit 7 to 4hex value in volts bit 3 to 0bcd value in 100 mv 1.8v (p+d)h = 46h 00c0h v ppf supply optimum program/erase voltage bit 7 to 4hex value in volts bit 3 to 0bcd value in 100 mv 12v offset data description value (p+e)h = 47h 0001h number of protection register fields in jedec id space. 0000h indicates that 256 fields are available. 1 (p+f)h = 48h 0080h protection field 1: protection description bits 0-7 lower byte of protection register address bits 8-15 upper byte of protection register address bits 16-23 2 n bytes in factory pre-programmed region bits 24-31 2 n bytes in user programmable region 0080h (p+10)h = 49h 0000h (p+11)h = 4ah 0003h 8 bytes (p+12)h= 4bh 0004h 16 bytes offset data description value (p+13)h = 4ch 0003h page-mode read capability bits 0-7 n such that 2 n hex value represents the number of read- page bytes. see offset 28h for device word width to determine page-mode data output width. 8 bytes (p+14)h = 4dh 0003h number of synchronous mode read configuration fields that follow. 3 (p+15)h = 4eh 0001h synchronous mode read capability configuration 1 bit 3-7 reserved bit 0-2 n such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the devices burstable address space. this fields 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data output width. 4 (p+16)h = 4fh 0002h synchronous mode read capability configuration 2 8 (p+17)h = 50h 0007h synchronous mode read capability configuration 3 cont. m36wt864tf (top) m36wt864bf (bottom) description offset data offset data (p+18)h =51h 02h (p+18)h =51h 02h number of bank regions within the device offset data description value
73/92 m36wt864tf, m36wt864bf table 42. bank and erase block region 1 information m36wt864tf (top) m36wt864bf (bottom) description offset data offset data (p+19)h =52h 0fh (p+19)h =52h 01h number of identical banks within bank region 1 (p+1a)h =53h 00h (p+1a)h =53h 00h (p+1b)h =54h 11h (p+1b)h =54h 11h number of program or erase operations allowed in region 1: bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+1c)h =55h 00h (p+1c)h =55h 00h number of program or erase operations allowed in other banks while a bank in same region is programming bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+1d)h =56h 00h (p+1d)h =56h 00h number of program or erase operations allowed in other banks while a bank in this region is erasing bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+1e)h =57h 01h (p+1e)h =57h 02h types of erase block regions in region 1 n = number of erase block regions with contiguous same-size erase blocks. symmetrically blocked banks have one blocking region. (2) (p+1f)h =58h 07h (p+1f)h =58h 07h bank region 1 erase block type 1 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+20)h =59h 00h (p+20)h =59h 00h (p+21)h =5ah 00h (p+21)h =5ah 20h (p+22)h =5bh 01h (p+22)h =5bh 00h (p+23)h =5ch 64h (p+23)h =5ch 64h bank region 1 (erase block type 1) minimum block erase cycles 1000 (p+24)h =5dh 00h (p+24)h =5dh 00h (p+25)h =5eh 01h (p+25)h =5eh 01h bank region 1 (erase block type 1): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for internal ecc used bits 5-7: reserved 5eh 01 5eh 01 (p+26)h =5fh 03h (p+26)h =5fh 03h bank region 1 (erase block type 1): page mode and synchronous mode capabilities bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved (p+27)h =60h 06h bank region 1 erase block type 2 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+28)h =61h 00h (p+29)h =62h 00h (p+2a)h =63h 01h (p+2b)h =64h 64h bank region 1 (erase block type 2) minimum block erase cycles 1000 (p+2c)h =65h 00h
m36wt864tf, m36wt864bf 74/92 note: 1. the variable p is a pointer which is defined at cfi offset 15h. 2. bank regions. there are two bank regions, 1 contains all the banks that are made up of main blocks only, 2 contains the banks that are made up of the parameter and main blocks. table 43. bank and erase block region 2 information (p+2d)h =66h 01h bank regions 1 (erase block type 2): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for internal ecc used bits 5-7: reserved (p+2e)h =67h 03h bank region 1 (erase block type 2): page mode and synchronous mode capabilities bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved m36wt864tf (top) m36wt864bf (bottom) description offset data offset data (p+27)h =60h 01h (p+2f)h =68h 0fh number of identical banks within bank region 2 (p+28)h =61h 00h (p+30)h =69h 00h (p+29)h =62h 11h (p+31)h =6ah 11h number of program or erase operations allowed in bank region 2: bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+2a)h =63h 00h (p+32)h =6bh 00h number of program or erase operations allowed in other banks while a bank in this region is programming bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+2b)h =64h 00h (p+33)h =6ch 00h number of program or erase operations allowed in other banks while a bank in this region is erasing bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+2c)h =65h 02h (p+34)h =6dh 01h types of erase block regions in region 2 n = number of erase block regions with contiguous same-size erase blocks. symmetrically blocked banks have one blocking region. (2) (p+2d)h =66h 06h (p+35)h =6eh 07h bank region 2 erase block type 1 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+2e)h =67h 00h (p+36)h =6fh 00h (p+2f)h =68h 00h (p+37)h =70h 00h (p+30)h =69h 01h (p+38)h =71h 01h (p+31)h =6ah 64h (p+39)h =72h 64h bank region 2 (erase block type 1) minimum block erase cycles 1000 (p+32)h =6bh 00h (p+3a)h =73h 00h (p+33)h =6ch 01h (p+3b)h =74h 01h bank region 2 (erase block type 1): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for internal ecc used bits 5-7: reserved m36wt864tf (top) m36wt864bf (bottom) description offset data offset data
75/92 m36wt864tf, m36wt864bf note: 1. the variable p is a pointer which is defined at cfi offset 15h. 2. bank regions. there are two bank regions, region 1 contains all the banks that are made up of main blocks only, region 2 con- tains the banks that are made up of the parameter and main blocks. (p+34)h =6dh 03h (p+3c)h =75h 03h bank region 2 (erase block type 1): page mode and synchronous mode capabilities (defined in table 10) bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved (p+35)h =6eh 07h bank region 2 erase block type 2 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+36)h =6fh 00h (p+37)h =70h 02h (p+38)h =71h 00h (p+39)h =72h 64h bank region 2 (erase block type 2) minimum block erase cycles 1000 (p+3a)h =73h 00h (p+3b)h =74h 01h bank region 2 (erase block type 2): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for internal ecc used bits 5-7: reserved (p+3c)h =75h 03h bank region 2 (erase block type 2): page mode and synchronous mode capabilities (defined in table 10) bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved (p+3d)h =76h (p+3d)h =76h feature space definitions (p+3e)h =77h (p+3e)h =77h reserved m36wt864tf (top) m36wt864bf (bottom) description offset data offset data
m36wt864tf, m36wt864bf 76/92 appendix c. flash flowcharts and pseudo codes figure 28. program flowchart and pseudo code note: 1. status check of sr1 (protected block), sr3 (v pp (v ppf ) invalid) and sr4 (program error) can be made after each program oper- ation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase controller operations. write 40h or 10h ai06170 start write address & data read status register yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) program_command (addresstoprogram, datatoprogram) {: writetoflash (bank_address, 0x40) ; /*or writetoflash (bank_address, 0x10) ; */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*vpp invalid error */ error_handler ( ) ; yes end yes no sr1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
77/92 m36wt864tf, m36wt864bf figure 29. double word program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v pp (v ppf ) invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase operations. 3. address 1 and address 2 must be consecutive addresses differing only for bit a0. write 30h ai06171 start write address 1 & data 1 (3) read status register yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) yes end yes no sr1 = 0 program to protected block error (1, 2) write address 2 & data 2 (3) double_word_program_command (addresstoprogram1, datatoprogram1, addresstoprogram2, datatoprogram2) { writetoflash (bank_address, 0x30) ; writetoflash (addresstoprogram1, datatoprogram1) ; /*see note (3) */ writetoflash (addresstoprogram2, datatoprogram2) ; /*see note (3) */ /*memory enters read status state after the program command*/ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.b7== 0) ; if (status_register.sr3==1) /*vpp invalid error */ error_handler ( ) ; if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
m36wt864tf, m36wt864bf 78/92 figure 30. quadruple word program flowchart and pseudo code note: 1. status check of sr1 (protected block), sr3 (v pp (v ppf ) invalid) and sr4 (program error) can be made after each program oper- ation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase operations. 3. address 1 to address 4 must be consecutive addresses differing only for bits a0 and a1. write 56h ai06977 start write address 1 & data 1 (3) read status register yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) yes end yes no sr1 = 0 program to protected block error (1, 2) write address 2 & data 2 (3) quadruple_word_program_command (addresstoprogram1, datatoprogram1, addresstoprogram2, datatoprogram2, addresstoprogram3, datatoprogram3, addresstoprogram4, datatoprogram4) { writetoflash (bank_address, 0x56) ; writetoflash (addresstoprogram1, datatoprogram1) ; /*see note (3) */ writetoflash (addresstoprogram2, datatoprogram2) ; /*see note (3) */ writetoflash (addresstoprogram3, datatoprogram3) ; /*see note (3) */ writetoflash (addresstoprogram4, datatoprogram4) ; /*see note (3) */ /*memory enters read status state after the program command*/ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.b7== 0) ; if (status_register.sr3==1) /*vpp invalid error */ error_handler ( ) ; if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr==1) /*program to protect block error */ error_handler ( ) ; } write address 3 & data 3 (3) write address 4 & data 4 (3)
79/92 m36wt864tf, m36wt864bf figure 31. program suspend & resume flowchart and pseudo code write 70h ai06173 read status register yes no sr7 = 1 yes no sr2 = 1 program continues write d0h read data from another address start write b0h program complete write ffh read data program_suspend_command ( ) { writetoflash (any_address, 0xb0) ; writetoflash (bank_address, 0x70) ; /* read status register to check if program has already completed */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr2==0) /*program completed */ { writetoflash (bank_address, 0xff) ; read_data ( ) ; /*read data from another block*/ /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (bank_address, 0xff) ; read_data ( ); /*read data from another address*/ writetoflash (any_address, 0xd0) ; /*write 0xd0 to resume program*/ } } write ffh
m36wt864tf, m36wt864bf 80/92 figure 32. block erase flowchart and pseudo code note: if an error is found, the status register must be cleared before further program/erase operations. write 20h ai06174 start write block address & d0h read status register yes no sr7 = 1 yes no sr3 = 0 yes sr4, sr5 = 1 v pp invalid error (1) command sequence error (1) no no sr5 = 0 erase error (1) end yes no sr1 = 0 erase to protected block error (1) yes erase_command ( blocktoerase ) { writetoflash (bank_address, 0x20) ; writetoflash (blocktoerase, 0xd0) ; /* only a12-a20 are significannt */ /* memory enters read status state after the erase command */ } while (status_register.sr7== 0) ; do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ if (status_register.sr3==1) /*vpp invalid error */ error_handler ( ) ; if ( (status_register.sr4==1) && (status_register.sr5==1) ) /* command sequence error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; if ( (status_register.sr5==1) ) /* erase error */ error_handler ( ) ; }
81/92 m36wt864tf, m36wt864bf figure 33. erase suspend & resume flowchart and pseudo code write 70h ai06175 read status register yes no sr7 = 1 yes no sr6 = 1 erase continues write d0h read data from another block or program/protection program or block protect/unprotect/lock start write b0h erase complete write ffh read data write ffh erase_suspend_command ( ) { writetoflash (bank_address, 0xb0) ; writetoflash (bank_address, 0x70) ; /* read status register to check if erase has already completed */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr6==0) /*erase completed */ { writetoflash (bank_address, 0xff) ; read_data ( ) ; /*read data from another block*/ /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (bank_address, 0xff) ; read_program_data ( ); /*read or program data from another address*/ writetoflash (bank_address, 0xd0) ; /*write 0xd0 to resume erase*/ } }
m36wt864tf, m36wt864bf 82/92 figure 34. locking operations flowchart and pseudo code write 01h, d0h or 2fh ai06176 read block lock states yes no locking change confirmed? start write 60h locking_operation_command (address, lock_operation) { writetoflash (bank_address, 0x60) ; /*configuration setup*/ if (readflash (address) ! = locking_state_expected) error_handler () ; /*check the locking state (see read block signature table )*/ writetoflash (bank_address, 0xff) ; /*reset to read array mode*/ } write ffh write 90h end if (lock_operation==lock) /*to protect the block*/ writetoflash (address, 0x01) ; else if (lock_operation==unlock) /*to unprotect the block*/ writetoflash (address, 0xd0) ; else if (lock_operation==lock-down) /*to lock the block*/ writetoflash (address, 0x2f) ; writetoflash (bank_address, 0x90) ;
83/92 m36wt864tf, m36wt864bf figure 35. protection register program flowchart and pseudo code note: 1. status check of sr1 (protected block), sr3 (v pp (v ppf ) invalid) and sr4 (program error) can be made after each program oper- ation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase controller operations. write c0h ai06177 start write address & data read status register yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) protection_register_program_command (addresstoprogram, datatoprogram) {: writetoflash (bank_address, 0xc0) ; do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*vpp invalid error */ error_handler ( ) ; yes end yes no sr1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
m36wt864tf, m36wt864bf 84/92 figure 36. enhanced factory program flowchart write 30h address wa1 ai06160 start read status register yes no sr0 = 0? end write d0h address wa1 write pd1 address wa1 write pd2 address wa2 ( 1) yes no read status register write pdn address wan ( 1) yes no read status register read status register no write pd1 address wa1 ( 1) write pdn address wan ( 1) no read status register write ffffh address block wa1 setup phase verify phase sr0 = 0? sr0 = 0? sr0 = 0? sr0 = 0? read status register yes no sr0 = 0? write ffffh address block wa1 sr7 = 0? yes no check sr4, sr3 and sr1 for program, v pp and lock errors exit read status register no write pd2 address wa2 ( 1) sr0 = 0? yes read status register sr7 = 1? check status register for errors yes no yes yes note 1. address can remain starting address wa1 or be incremented. program phase exit phase = / / =
85/92 m36wt864tf, m36wt864bf enhanced factory program pseudo code efp_command(addressflow,dataflow,n) /* n is the number of data to be programmed */ { /* setup phase */ writetoflash(addressflow[0],0x30); writetoflash(addressflow[0],0xd0); status_register=readflash(any_address); if (status_register.b7==1){ /*efp aborted for an error*/ if (status_register.b4==1) /*program error*/ error_handler(); if (status_register.b3==1) /*vpp invalid error*/ error_handler(); if (status_register.b1==1) /*program to protect block error*/ error_handler(); } else{ /*program phase*/ do{ status_register=readflash(any_address); /* e or g must be toggled*/ } while (status_register.b0==1) /*ready for first data*/ for (i=0; i++; i< n){ writetoflash(addressflow[i],dataflow[i]); /* status register polling*/ do{ status_register=readflash(any_address); /* e or g must be toggled*/ } while (status_register.b0==1); /* ready for a new data */ } writetoflash(another_block_address,ffffh); /* verify phase */ for (i=0; i++; i< n){ writetoflash(addressflow[i],dataflow[i]); /* status register polling*/ do{ status_register=readflash(any_address); /* e or g must be toggled*/ } while (status_register.b0==1); /* ready for a new data */ } writetoflash(another_block_address,ffffh); /* exit program phase */ /* exit phase */ /* status register polling */ do{ status_register=readflash(any_address); /* e or g must be toggled */ } while (status_register.b7==0); if (status_register.b4==1) /*program failure error*/ error_handler(); if (status_register.b3==1) /*vpp invalid error*/ error_handler(); if (status_register.b1==1) /*program to protect block error*/ error_handler(); } }
m36wt864tf, m36wt864bf 86/92 figure 37. quadruple enhanced factory program flowchart write 75h address wa1 ai06178 start read status register yes no sr0 = 0? end write pd1 address wa1 ( 1) write pd2 address wa2 ( 2) yes no read status register write pd3 address wa3 ( 2) yes no read status register read status register setup phase program and verify phase sr0 = 0? sr0 = 0? sr7 = 0? yes no check sr4, sr3 and sr1 for program, v pp and lock errors exit check status register for errors yes note 1. address can remain starting address wa1 (in which case the next page is programmed) or can be any address in the same block. 2.the address is only checked for the first word of each page as the order to program the words is fixed so subsequent words in each page can be written to any address. load phase exit phase write pd4 address wa4 ( 2) sr0 = 0? last page? yes no write ffffh address block wa1 write pd1 address wa1 read status register no first load phase = /
87/92 m36wt864tf, m36wt864bf quadruple enhanced factory program pseudo code quad_efp_command(addressflow,dataflow,n) /* n is the number of pages to be programmed.*/ { /* setup phase */ writetoflash(addressflow[0],0x75); for (i=0; i++; i< n){ /*data load phase*/ /*first data*/ writetoflash(addressflow[i],dataflow[i,0]); /*at the first data of the first page, quad-efp may be aborted*/ if (first_page) { status_register=readflash(any_address); if (status_register.b7==1){ /*efp aborted for an error*/ if (status_register.b4==1) /*program error*/ error_handler(); if (status_register.b3==1) /*vpp invalid error*/ error_handler(); if (status_register.b1==1) /*program to protect block error*/ error_handler(); } } /*2nd data*/ do{ status_register=readflash(any_address); /* e or g must be toggled*/ }while (status_register.b0==1) writetoflash(addressflow[i],dataflow[i,1]); /*3rd data*/ do{ status_register=readflash(any_address); /* e or g must be toggled*/ }while (status_register.b0==1) writetoflash(addressflow[i],dataflow[i,2]); /*4th data*/ do{ status_register=readflash(any_address); /* e or g must be toggled*/ }while (status_register.b0==1) writetoflash(addressflow[i],dataflow[i,3]); /* program&verify phase */ do{ status_register=readflash(any_address); /* e or g must be toggled*/ }while (status_register.b0==1) } /* exit phase */ writetoflash(another_block_address,ffffh); /* status register polling */ do{ status_register=readflash(any_address); /* e or g must be toggled */ } while (status_register.b7==0); if (status_register.b1==1) /*program to protected block error*/ error_handler(); if (status_register.b3==1) /*vpp invalid error*/ error_handler(); if (status_register.b4==1) /*program failure error*/ error_handler(); } }
m36wt864tf, m36wt864bf 88/92 appendix d. flash command interface state tables table 44. command interface states - modify table, next state note: 1. ci = command interface, cr = configuration register, efp = enhanced factory program, quad efp = quadruple enhanced fac- tory program, dwp = double word program, qwp = quadruple word program, p/e. c. = program/erase controller. 2. at power-up, all banks are in read array mode. a read array command issued to a busy bank, results in undetermined data out- put. 3. the two cycle command should be issued to the same bank address. 4. if the p/e.c. is active, both cycles are ignored. 5. the clear status register command clears the status register error bits except when the p/e.c. is busy or suspended. 6. efp and quad efp are allowed only when status register bit sr0 is set to 0.efp and quad efp are busy if block address is first efp address. any other commands are treated as data. current ci state next ci state after command input read array (2) program wp setup (3,4) program dwp, qwp setup (3,4) block erase, bank erase setup (3,4) efp setup quad- efp setup erase confirm p/e resume, block unlock confirm, efp confirm program/ erase suspend read status register clear status register (5) read electronic signature, read cfi query ready ready program setup program setup erase setup efp setup quad-efp setup ready lock/cr setup ready (lock error) ready ready (lock error) otp setup otp busy busy program setup program busy busy program busy program suspended program busy suspend program suspended program busy program suspended erase setup ready (error) erase busy ready (error) busy erase busy erase suspended erase busy suspend erase suspended program in erase suspend erase suspended erase busy erase suspended program in erase suspend setup program in erase suspend busy busy program in erase suspend busy program in erase suspend suspended program in erase suspend busy suspend program in erase suspend suspended program in erase suspend busy program in erase suspend suspended lock/cr setup in erase suspend erase suspend (lock error) erase suspend erase suspend (lock error) efp setup ready (error) efp busy ready (error) busy efp busy (6) verify efp verify (6) quad efp setup quad efp busy (6) busy quad efp busy (6)
89/92 m36wt864tf, m36wt864bf table 45. command interface states - modify table, next output note: 1. ci = command interface, cr = configuration register, efp = enhanced factory program, quad efp = quadruple enhanced fac- tory program, dwp = double word program, qwp = quadruple word program, p/e. c. = program/erase controller. 2. at power-up, all banks are in read array mode. a read array command issued to a busy bank, results in undetermined data out- put. 3. the two cycle command should be issued to the same bank address. 4. if the p/e.c. is active, both cycles are ignored. 5. the clear status register command clears the status register error bits except when the p/e.c. is busy or suspended. 6. the output state shows the type of data that appears at the outputs if the bank address is the same as the command address. a bank can be placed in read array, read status register, read electronic signature or read cfi query mode, depending on the command issued. each bank remains in its last output state until a new command is issued. the next state does not depend on the banks output state. current ci state next output state after command input (6) read array (2) program dwp, qwp setup (3,4) block erase, bank erase setup (3,4) efp setup quad- efp setup erase confirm p/e resume, block unlock confirm, efp confirm program/ erase suspend read status register clear status register (5) read electronic signature, read cfi query program setup status register erase setup otp setup program in erase suspend efp setup efp busy efp verify quad efp setup quad efp busy lock/cr setup status register lock/cr setup in erase suspend otp busy array status register output unchanged status register output unchanged status register ready array status register output unchanged status register output unchanged electronic signature/ cfi program busy erase busy program/erase program in erase suspend busy program in erase suspend suspended
m36wt864tf, m36wt864bf 90/92 table 46. command interface states - lock table, next state note: 1. ci = command interface, cr = configuration register, efp = enhanced factory program, quad efp = quadruple enhanced fac- tory program, p/e. c. = program/erase controller. 2. efp and quad efp are allowed only when status register bit sr0 is set to 0. efp and quad efp are busy if block address is first efp address. any other commands are treated as data. 3. efp and quad efp exit when block address is different from first block address and data is ffffh. 4. if the p/e.c. is active, both cycles are ignored. 5. illegal commands are those not defined in the command set. current ci state next ci state after command input lock/cr setup (4) otp setup (4) block lock confirm block lock-down confirm set cr confirm efp exit, quad efp exit (3) illegal command (5) p/e. c. operation completed ready lock/cr setup otp setup ready n/a lock/cr setup ready (lock error) ready ready (lock error) n/a otp setup otp busy n/a busy ready program setup program busy n/a busy program busy ready suspend program suspended n/a erase setup ready (error) n/a busy erase busy ready suspend lock/cr setup in erase suspend erase suspended n/a program in erase suspend setup program in erase suspend busy n/a busy program in erase suspend busy erase suspended suspend program in erase suspend suspended n/a lock/cr setup in erase suspend erase suspend (lock error) erase suspend erase suspend (lock error) n/a efp setup ready (error) n/a busy efp busy (2) efp verify efp busy (2) n/a verify efp verify (2) ready efp verify (2) ready quadefp setup quad efp busy (2) n/a busy quad efp busy (2) ready quad efp busy (2) ready
91/92 m36wt864tf, m36wt864bf table 47. command interface states - lock table, next output note: 1. ci = command interface, cr = configuration register, efp = enhanced factory program, quad efp = quadruple enhanced fac- tory program, p/e. c. = program/erase controller. 2. efp and quad efp exit when block address is different from first block address and data is ffffh. 3. if the p/e.c. is active, both cycles are ignored. 4. illegal commands are those not defined in the command set. current ci state next output state after command input lock/cr setup (3) otp setup (3) block lock confirm block lock-down confirm set cr confirm efp exit, quad efp exit (2) illegal command (4) p/e. c. operation completed program setup status register output unchanged erase setup otp setup program in erase suspend efp setup efp busy efp verify quad efp setup quad efp busy lock/cr setup status register array status register output unchanged lock/cr setup in erase suspend otp busy status register output unchanged array output unchanged output unchanged ready status register output unchanged array output unchanged output unchanged program busy erasebusy program/erase program in erase suspend busy program in erase suspend suspended
m36wt864tf, m36wt864bf 92/92 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unite d states. www.st.com

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